Nov 21, 2007
删除文本文件中包含特定字符串所在行[script tips]
grep
-v, --invert-match select non-matching lines
grep -v "string" tee tmp.file
mv -f tmp.file original.file
or
vi
:g/string/d
0
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script,
Tips
Nov 20, 2007
[转]What is the difference between FPGA and ASIC?
- This question is very popular in VLSI fresher interviews. It looks simple but a deeper insight into the subject reveals the fact that there are lot of thinks to be understood !! So here is the answer.
- Difference between ASICs and FPGAs mainly depends on costs, tool availability, performance and design flexibility. They have their own pros and cons but it is designers responsibility to find the advantages of the each and use either FPGA or ASIC for the product. However, recent developments in the FPGA domain are narrowing down the benefits of the ASICs.
- Field Programable Gate Arrays
- Faster time-to-market: No layout, masks or other manufacturing steps are needed for FPGA design. Readymade FPGA is available and burn your HDL code to FPGA ! Done !!
- No NRE (Non Recurring Expenses): This cost is typically associated with an ASIC design. For FPGA this is not there. FPGA tools are cheap. (sometimes its free ! You need to buy FPGA.... thats all !). ASIC youpay huge NRE and tools are expensive. I would say "very expensive"...Its in crores....!!
- Simpler design cycle: This is due to software that handles much of the routing, placement, and timing. Manual intervention is less.The FPGA design flow eliminates the complex and time-consuming floorplanning, place and route, timing analysis.
- More predictable project cycle: The FPGA design flow eliminates potential re-spins, wafer capacities, etc of the project since the design logic is already synthesized and verified in FPGA device.
- Field Reprogramability: A new bitstream ( i.e. your program) can be uploaded remotely, instantly. FPGA can be reprogrammed in a snap while an ASIC can take $50,000 and more than 4-6 weeks to make the same changes. FPGA costs start from a couple of dollars to several hundreds or more depending on the hardware features.
- Reusability: Reusability of FPGA is the main advantage. Prototype of the design can be implemented on FPGA which could be verified for almost accurate results so that it can be implemented on an ASIC. Ifdesign has faults change the HDL code, generate bit stream, program to FPGA and test again.Modern FPGAs are reconfigurable both partially and dynamically.
- FPGAs are good for prototyping and limited production.If you are going to make 100-200 boards it isn't worth to make an ASIC.
- Generally FPGAs are used for lower speed, lower complexity and lower volume designs.But today's FPGAs even run at 500 MHz with superior performance. With unprecedented logic density increases and a host of other features, such as embedded processors, DSP blocks, clocking, and high-speed serial at ever lower price, FPGAs are suitable for almost any type of design.
- Unlike ASICs, FPGA's have special hardwares such as Block-RAM, DCM modules, MACs, memories and highspeed I/O, embedded CPU etc inbuilt, which can be used to get better performace. Modern FPGAs are packed with features. Advanced FPGAs usually come with phase-locked loops, low-voltage differential signal, clock data recovery, more internal routing, high speed, hardware multipliers for DSPs, memory,programmable I/O, IP cores and microprocessor cores. Remember Power PC (hardcore) and Microblaze (softcore) in Xilinx and ARM (hardcore) and Nios(softcore) in Altera. There are FPGAs available now with built in ADC ! Using all these features designers can build a system on a chip. Now, dou yo really need an ASIC ?
- FPGA sythesis is much more easier than ASIC.
- In FPGA you need not do floor-planning, tool can do it efficiently. In ASIC you have do it.
- Powe consumption in FPGA is more. You don't have any control over the power optimization. This is where ASIC wins the race !
- You have to use the resources available in the FPGA. Thus FPGA limits the design size.
- Good for low quantity production. As quantity increases cost per product increases compared to the ASIC implementation.
- Application Specific Intergrated Circiut
- Cost....cost....cost....Lower unit costs: For very high volume designs costs comes out to be very less. Larger volumes of ASIC design proves to be cheaper than implementing design using FPGA.
- Speed...speed...speed....ASICs are faster than FPGA: ASIC gives design flexibility. This gives enoromous opportunity for speed optimizations.
- Low power....Low power....Low power: ASIC can be optimized for required low power. There are several low power techniques such as power gating, clock gating, multi vt cell libraries, pipelining etc are available to achieve the power target. This is where FPGA fails badly !!! Can you think of a cell phone which has to be charged for every call.....never.....low power ASICs helps battery live longer life !!
- In ASIC you can implement analog circuit, mixed signal designs. This is generally not possible in FPGA.
- In ASIC DFT (Design For Test) is inserted. In FPGA DFT is not carried out (rather for FPGA no need of DFT !) .
- Time-to-market: Some large ASICs can take a year or more to design. A good way to shorten development time is to make prototypes using FPGAs and then switch to an ASIC.
- Design Issues: In ASIC you should take care of DFM issues, Signal Integrity isuues and many more. In FPGA you don't have all these because ASIC designer takes care of all these. ( Don't forget FPGA isan IC and designed by ASIC design enginner !!)
- Expensive Tools: ASIC design tools are very much expensive. You spend a huge amount of NRE.
- Structured ASICs have the bottom metal layers fixed and only the top layers can be designed by the customer.
- Structured ASICs are custom devices that approach the performance of today's Standard Cell ASIC while dramatically simplifying the design complexity.
- Structured ASICs offer designers a set of devices with specific, customizable metal layers along with predefined metal layers, which can contain the underlying pattern of logic cells, memory, and I/O.
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AsicDeisgn,
fpga
Nov 14, 2007
a new gmail account for file sharing
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blog
Nov 10, 2007
Google搜索在工作上的应用技巧[ 转]
一、限定搜索范围的技巧
1、文件类型
有时候我们可能不需要搜索网页文件或者图片，我们可能想要搜索其他类型的问题，比如文档文件（Word，Excel，PPT），Flash文件，甚至是Google地图文件，我们都可以使用"filetype"功能来实现。
比如我想搜索一篇关于最新加密技术的Word论文，使用Google搜索"filetype:doc 加密技术 "即可得到大量相关信息。我想搜索关于中国的Google Earth卫星图片，那么就在Google中搜索"filetype:kmz china"即可。
2、指定网站
有时我们进行网页搜索，想要在某一个指定的网站内搜索感兴趣的内容，这时候我们可以使用"site"功能来限定搜索的网站。
比如，我想在新浪网上搜索关于世界杯赛程的消息，只需要用Google搜索"site:sina.com.cn 世界杯赛程"即可得到结果。
如果你想把搜索结果限制在大学的网站之中，可以使用"site:.edu 关键词"。
通过限定搜索范围的方法，我们可以更快更准确的搜索到我们想要的东西。
3、其他限定搜索方法
intitle：搜索关键词（intitle:关键字）只搜索网页标题含有关键词的页面。
inurl：搜索关键词（intitle:关键字）只搜索网页链接含有关键词的页面。
intext：搜索关键词（intext:关键字）只搜索网页body标签中的文本含有关键词的页面。
二、写作辅助小工具
Google有一些小工具，为我们的日常工作学习提供了很多方便之处。
1、翻译工具
Google本身带有中英文翻译的功能，只需输入一个关键词("翻译"或"fy"任选其一）和要查的中（英）文单词，Google会直接显示您要查的单词的英文（或中文）翻译。
比如我们想要翻译"香蕉"这个词为英文，那么只需要在Google中搜索"翻译 香蕉"或者"fy 香蕉"，返回的第一条记录就是翻译的结果。同样，我们搜索"fy banana"可以得到这个单词的中文翻译。
2、学术词典工具
我们有时候想要知道一个具体词汇的定义，可以使用"定义"或"define"，接着键入一个空格，然后键入您需要其定义的词。
比如，我们想要知道氨基酸是什么意思，只需要在Google中搜索"定义 氨基酸"，就可以找到氨基酸的定义。
三、改进工作效率
做为一个公司员工，每天都要关注自己公司和竞争对手的最新消息，怎么才能在最短的时间内获得最多的信息呢？Google可以帮助你。
Google 快讯是Google的新闻定制自动发送，用户可以定制自己需要的内容，Google会在设定的时间内（即时、每天、每周）给用户发送Google最新搜索到的新闻文章，非常方便，我们就可以用这个功能来跟踪自己公司和竞争对手的最新消息。
例如我是一家做搜索的开发公司，我需要每天关注自己的竞争对手，因此我只要登录：http://www.google.com/alerts?hl=zh-CN，然后在"搜索字词"中输入"Google"，"频率"为每天，即可每天收到关于Google的最新消息，同样在"搜索字词"中输入"百度"，可以获得百度的最新消息。
当然，搜索关键字不只是公司，开动我们的脑筋，我们可以用这个工具跟踪任何信息，比如输入某个名人的名字，可以追踪这个名人的最新消息和新闻，搜索某个行业名称，可以追踪这个行业的相关新闻，搜索某个新闻事件，可以得到这个事件的最新报道。
因此，我们只要灵活掌握和运行Google的搜索技巧，那会给自己的工作和学习带来相当大的提升，使得自己的事业能够更上一层楼。
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Docs
Nov 6, 2007
blog backup
没能找到快捷的办法直接从那个blog直接导入到这里，只好一篇篇手工copy，终于把http://www.yanzhi.org/blog/的文章copy过来了，这里仅此是作为它的一个备份，因为那边经常出现不能正常访问的情况，而且在国外访问速度较慢。
但由于blogspot在国内随时有着被封的危险，故还是以自己的虚拟主机空间为主体。
此后所有更新在两边同步进行。
http://www.yanzhi.org/blog/
http://digital-ic-design.blogspot.com/
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blog
Some Testing Glossary
[From http://digitalelectronics.blogspot.com/2007/10/some-testing-glossary.html ]
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AsicDeisgn
set false path
A mistake in my work:
In the synthesis script, we use the script below to set false path between each clock.
set _all_clks [all_clocks];
foreach_in_collection _clk $_all_clks {
foreach_in_collection _other_clk [remove_from_collection $_all_clks $_clk] {
set_false_path -from $_clk -to $_other_clk;
}
}
However, there are two clocks with the same source(frenquence&phase) but different clock gatin cell , and we think they are the same in the design. So we need reset them.
reset_path -from A_CLK -to B_CLK;
reset_path -from B_CLK -to A_CLK;
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AsicDeisgn
Query Yourself before Architecting a Chip
[From:http://www.vlsichipdesign.com/askyourselfarchitect.html]
This article assuming you are an Architect and What all questions will come to your thought process before Architecting and making the Chip as a first-pass success. Chip Design is an Integration Challenge.
- What is the targetted market for this Chip.
- What are the competitor's to this Chip and Market Requirement and ROI
- What is the Fabrication Unit the Chip is targetted for?
- What is the Success rate and Yield numbers achieved in the Fabrication Unit
- What is the technology Process targetted for
- What is the correlation of the library models w.r.t. Silicon
- What are the various Protocols the Chip is going to address
- Hardware & Software Parti-tioning.
- What is the processor/micro-controller suitable for this application.
- What is the bus-architecture targetted
- What is the performance targets for this bus architecture
- What are the various Interfaces the Chip is having
- Is the design going to be in single Vt or with Multi-Vt design
- Is using Embedded macro's right choice or Memory Macros
- What are the IP's are going to be Re-usued
- What are the IP's going to Hard-macro's
- What is the Verification Status and corner-case coverage of the I.P's
- What is the Die-size targetted/Estimated for the Chip
- What is the Power targets
- Is Power Management Unit a requirement in the chip to reduce Dynamic power
- What are the mechanisms followed to reduce the leakage power
- Is Module enables/clock-gating a part of the Methodology
- Is resets going to synchronous or asynchronous
- What are the various Synchronous Mechanisms for data-transfer's
- How many clock-domains required for the Chip
- How many PLL's are required or single PLL sufficient for all the clocks required
- What is the thought process behind PAD's Is LVTTL/SSTL pads
- Is the package going to wire-bond or Flip-chip
- Methodology for Optimal Power-grid design
- What are the noise reducing Mechanism's in case of analog integration
- Is there any requirement of speed monitor's or process checking blocks
- What is the type of fuses used laser fuse or efuses
- Is there any requirement of Fib Cells in the Design
- What are the mechanism's used to handle ESD
- what is the reliability target of the Chip and how it is addressed
- What are the Mechanisms used for Yield improvement
- Is the chip tested at at-speed test
- How much Memory-map is allocated for the IP's
- What is the metric for spare-gates in the Chip for ECO's
- Is repairable memories required
- What is the tester targetted and the requirement to the Chip in terms of Scan-chain
- Is test-vector compression mechanism's a requirement
- What is the PLL performance in terms of Jitter
- What is the Interrupt handling mechanism with in the Chip.
- What is the ROM-Code for the Chip.
- What is the Chip utilization targets
- Will the chip be routable or any requirement for special libraries with different routing tracks.
- What is the Methodology for tools and versions
- What is the Version control mechanism planned for data handling across multi Geographical Environments.
- What is the signoff criteria for the Chip
- What is the frequency targets for the Chip.
- Is there room for further revisions of the Chip.
- If the Chip has DDR/SDR interface is there any requirement for DLL.
- What are the limitations of the Tools interms of Complexity/run-times/turn-around times/Computation Power requirements.
- What is the Mechanisms/Steps taken for the various Variabilities in the Chip IR drop/Power ground noise/inductance effects/EMI noise/Package noise/Crosstalk noise/Simultaneous Switching noise/Channel length variation/On chip Variation/Inter die variations/Intra die Process variations.
1 Comments
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AsicDeisgn
On-Chip Variation(OCV) Analysis
On Chip Variations or inter-die variations could be caused due to :
• IR drop
• Vt variations
• Channel length variation
So the normal flow of qualifying the Timing with plain worst and best corners is no more enough.
To perform on-chip variation analysis, use the set_operating_conditions command.
Because on-chip variations consider that cells and nets can operate at slightly different operating conditions, you must consider a minimum value and a maximum value for each delay of the design.Specify two operating conditions to represent the lower and upper bounds of the operating condition for on-chip variation, keeping the following guidelines in mind.
• Each delay of the design has an uncertainty bounded by the minimum value (computed for the minimum operating condition) and maximum value (computed for the maximum operating condition).
• Minimum paths are computed using the delay of the minimum operating condition.
• Maximum paths are computed using the delay of the maximum operating condition.
Example 1
This command sequence performs timing analysis for on-chip variation 20 percent below the worst-case commercial (WCCOM)
operating condition. It also performs clock reconvergence pessimism removal for paths with positive slack.
pt_shell> set_operating_conditions -analysis_type on_chip_variation WCCOM
pt_shell> set_timing_derate -min 0.8 -max 1.0
Example 2
This command sequence performs timing analysis for on-chip variation between two predefined operating conditions:WCCOM_scaled andWCCOM.It also performsclock reconvergence pessimism removal for paths with slack less than 0.4 ns.
pt_shell> set_operating_conditions -analysis_type on_chip_variation \
? -min WCCOM_scaled -max WCCOM
pt_shell> report_timing -remove_clock_reconvergence_pessimism 0.4
Example 3
This command sequence performs timing analysis for on-chip variation 5 percent above and 10 percent below the SDF backannotated
cell delays. For net delays, the on-chip variation is between 2 percent above and 4 percent belowtheSDFback-annotated values.
For timing delays, the on-chip variation for timing checks is 10 percent above the SDF values for setup and 20 percent belowthe SDF values for hold checks.
pt_shell> read_sdf -analysis_type on_chip_variation my_design.sdf
pt_shell> set_timing_derate -cell -min 0.90 -max 1.05
pt_shell> set_timing_derate -net -min 0.96 -max 1.02
pt_shell> set_timing_derate -cell_check -min 0.80 -max 1.10
0
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AsicDeisgn
Synopsys Design Compiler-A quick Tutorial
From: http://www.vlsiip.com/dc_shell/
Step 0. Invoke Design Compiler
unix> dc_shell-t
Step 1. Setup technology library. To synthesize a design you need technology library which will contain
description of the cells from the fab, and their timing. This is usually a .db file found in
library installation directory. To do this
1(a). Tell synopsys where your <library>.db file is.
set search_path {/homes/amittal/s5/work/physical_lib/corelib/tsmc_090_g_art}
1(b). Tell synopsys what is your technology library, which you want to map your design on called
set target_library {scadv_tsmc_cln90g_lvt_ss_0p9v_125c.db}
1(c). Set up link libraries. This is optional .db files which are pre synthesized and ready to be read in
For this, append your search path where your optional .db files are
lappend search_path {[exec pwd]}
lappend search_path {.}
1(d). Set up link libraries. This is optional .db files which are pre synthesized and ready to be read in
set link_library {PLL10CCMID_W_125_1.35.db}
Step 2. Read In your design files
2(a). if it is verilog:
read_verilog counter.v
2(b). if it is vhdl: As it is in this tutorial
read_vhdl counter.vhd
read_vhdl counter_top.vhd
2(c). if it is ddc:
read_ddc counter.ddc
Step 3. Set Design Constraints:
3(a) Set frequency of operation: You have to create a clock in the design,
With a given timeperiod. The command below creates a clock and calls it
'design_clk' with a timeperiod of 10 ns, (100MHz), and maps it to the
'clk' input of the design.
create_clock -period 10 -name design_clk clk
3(b) Set input constraints : Set how much time would be spent by
signals arriving into your design, outside your design with respect to the clock
set_input_delay 4.0 [remove_from_collection [all_inputs ] clk] -clock design_clk
3(c) Set output constraints : Set how much time would be spent by
signals leaving your desing, outside your design, before they are captured by
the same clock
set_output_delay 7.0 [all_outputs] -clock design_clk
3(d) Set area constraints : set maximum allowed area to 0 :). well its just to
instruct design compiler that use as less area as possible.
set_max_area 0
Step 4. Enable clock gating for low power (optional)
4(a) The following commands will try to insert clock gates for each 2 registers
set_clock_gating_style -minimum_bitwidth 2
Step 5. Write formal verification setupfile (optional)
set_svf -append "counter.svf"
Step 6. Set Register optimization veriables (optional)
(a) Set automatic removal of constant flipflop(s)
set compile_seqmap_propagate_constants true
(b) Set automatic removal of unloaded flipflop(s)
set compile_delete_unloaded_sequential_cells false
Step 7. Set mapping of sync resets to aviod Xs in sims (optional)
set hdlin_ff_always_sync_set_reset "true"
Step 8. Set the name of top level as current design and compile the design
(a) current_design counter_top
compile -map_effort high
(b) If you are using dc ultra :
compile_ultra
You may want to turn off output inversion of sequential cells
compile_ultra -no_seq_output_inversion
Step 9. Write design output netlist
9(a).Write output in ddc format
write -format ddc -output counter.ddc -hier
9(b).Write output in verilog format
write -format ddc -output counter.vlog -hier
Step 10. You may want to flatten your design before writing out netlist
ungroup -all -flatten
write -format verilog -output counter_flat.vlog
Step 11. Writing a timing report of your design
report_timing > counter_timing.rep
Step 12. Quit Design Compiler
quit
More random DC shell Tcl mode Commands:
define_design_lib lib1 -path ~/misc/vhdl
analyze -library lib1 -format vhdl /homes/amittal/misc/vhdl/xx.vhdl
get_design_lib_path SYNTH
get_design_lib_path work
read_verilog mse.v
report_timing -delay max -from ARRAYCACHE_I/CACHEDIRRAM_I/regfile64x704_assembly_0/RA_ram[3] -to pCacheMemReqFifoDataOut
report_timing -delay max -through [find net ARRAYCACHE_I/CACHEDIRRAM_I/regfile64x704_assembly_0/RA_ram[3]]
report_constraint -verbose -all_violators
create_clock -name "myclk" -period 13 [get_ports pClk]
set_output_delay 1.0 -clock [get_clocks myclk] pCacheMemReqFifoDataOut[161]
set_wire_load_mode segmented
set_wire_load_mode enclosed
update_timing
report_timing -from [find pin ARRAYCACHE_I/LatencyReqReg*/Q] -to pCacheMemReqFifoDataOut
report_timing -from [find pin ARRAYCACHE_I/CACHE_DATA_RAM/DO*] -to pCacheMemReqFifoDataOut
set_output_delay 1.0 -clock myclk pCacheMemReqFifoDataOut
set_false_path -through [find pin ARRAYCACHE_I/FracSetReg*/*]index
It is to be noted that if there are no constraints, 'set_false_path' does not actually works.
I tried to find delays to a output port, without any constraints, form a known point in the design.
I got that.
Then I wanted to find next worst path to that output port, to I set a false path on the path found above.
But it wouldn't work
I then created a clcok and constrainted the output port,
!! False path worked.... magic :)
create_clock -period 4.8 -name vclk
set_input_delay 2.5 pDmaReadRegIndex -clock vclk -add_delay
set_output_delay 2.5 pInsertNopOut -clock vclk -add_delay
set_false_path -from vclk -to PESWITCH_pClk
set_false_path -from PESWITCH_pClk -to vclk
set_false_path -from PESWITCH_pClk -through pDmaReadRegIndex -to pInsertNopOut
report_timing -from pDmaReadRegIndex -to pInsertNopOut
set_input_delay [expr 0.35*$vclk_period] [all_inputs] -clock vclk -add_delay
set_output_delay [expr 0.35*$vclk_period] [all_outputs] -clock vclk -add_delay
set_false_path -from PESWITCH_pClk -through [all_inputs] -to [all_outputs]
set compile_log_format "%elap_time %area %wns %tns %drc %endpoint %group_path"
1 Comments
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AsicDeisgn
Handle Unconnected Pins in Design Compiler
Question:
The original Verilog code snippet is as follows:
module sub ( C, z );
input C;
output z;
AN3 U1 ( .A(), .B(), .C(C), .Z(z) );
endmodule
In the dumped Verilog, the code is as follows:
module sub ( C, z );
input C;
output z;
AN3 U1 ( .A(1'b0), .B(1'b0), .C(C), .Z(z) );
endmodule
Why does Design Compiler connect unconnected pins to 0?
Because Design Compiler does not allow a floating input of a cell, an
unconnected input will always be tied to '0' or '1'.
So in the dumped Verilog, you can see the unconnected pin A connected to 0,
But from version Z-2007.03-SP1, the behavior is different. Check the dumped
Verilog; it is similar to the following:
=============================
wire net1, net2;
MUX2D1 U1 ( .I0(net1), .I1(net2),.C(C), .Z(z) );
Notice the difference in the generated Verilog between versions
Y-2006.06 and Z-2007.03.
1 Comments
标签：
AsicDeisgn
Wire Load Model
Defining Wire Load Models
Wire load modeling allows you to estimate the effect of wire length and fanout on the resistance, capacitance, and area of nets. Design Compiler uses these physical values to calculate wire delays and circuit speeds. Semiconductor vendors develop wire load models, based on statistical information specific to the vendors' process. The models
include coefficients for area, capacitance, and resistance per unit length, and a fanout-to-length table for estimating net lengths (the number of fanouts determines a nominal length).
Note:
You can also develop custom wire load models.
Wire load models estimate the effect of wire length on design performance. It should be speicfied when define the design environment.
Determining Available Wire Load Models
Use the report_lib command to list the wire load models defined in a technology library. The library must be loaded in memory before you run the report_lib command.
eg:
dc_shell-xg-t> read_file my_lib.db
Example Wire Load Models Report
****************************************
Report : library
Library: my_lib
Version: Y-2006.06
Date : Mon May 1 10:56:49 2006
****************************************
...
Wire Loading Model:
Name : 05x05
Location : my_lib
Resistance : 0
Capacitance : 1
Area : 0
Slope : 0.186
Fanout Length Points Average Cap Std Deviation
------------------------------------------------------------------------
1 0.39
Name : 10x10
Location : my_lib
Resistance : 0
Capacitance : 1
Area : 0
Slope : 0.311
Fanout Length Points Average Cap Std Deviation
------------------------------------------------------------------------
1 0.53
...
Specifying Wire Load Models and Modes
The default_wire_load library attribute identifies the default wire load model for a technology library.To change the wire load model or mode specified in a technology library, use the set_wire_load_model and set_wire_load_mode commands.
eg:
dc_shell-xg-t> set_wire_load_model "10x10"
dc_shell-xg-t> set_wire_load_mode enclosed
If you need more detail infomation about wire_load_model,please refer the Design Compiler Usage.
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AsicDeisgn
Why we should do gate-level simulation?[转]
Matt Weber
Jason Pecor
Silicon Logic Engineering
In a recent ESNUG article ( http://www.deepchip.com/items/0421-01.html), eighteen engineers shared their view of the current usefulness of gate level simulation. Only one of those engineers has completely removed gate level simulation from their design flow. The other engineers listed many reasons for continuing to do some level of gate level simulation.
1. Since scan and other test structures are added during and after synthesis, they are not checked by the rtl simulations and therefore need to be verified by gate level simulation.
2. Static timing analysis tools do not check asynchronous interfaces, so gate level simulation is required to look at the timing of these interfaces.
3. Careless wildcards in the static timing constraints set false path or mutlicycle path constraints where they don't belong.
4. Design changes, typos, or misunderstanding of the design can lead to incorrect false paths or multicycle paths in the static timing constraints.
5. Using create_clock instead of create_generated_clock leads to incorrect static timing between clock domains.
6. Gate level simulation can be used to collect switching factor data for power estimation.
7. X's in RTL simulation can be optimistic or pessimistic. The best way to verify that the design does not have any unintended dependence on initial conditions is to run gate level simulation.
8. It's a nice "warm fuzzy" that the design has been implemented correctly.
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A IPcore Introduction[just as a template]
BodaHx8 - MPEG-2 MP + H.264 HP + VC-1 AP + MPEG-4 ASP (DivX) + RV8/9/10 + JPEG codec (1920*1080*30)
Overview
Chips&Media's BodaHx8 is a high-performance and optimally-unified multi-standard decoder IP that performs three major decoding functionalities such as H.264, MPEG-2, MPEG-4 (DivX), RV8/9/10, JPEG codec and VC-1 up to HD resolution at 30 frames per second. Under our technologies, BodaHx8 needs ultra low-power and ultra low clock frequency based on Chips&Media's advanced video decoding hardware architecture, while BodaHx8 provides decent flexibility in error concealment, error resilient, and multi-resolution/multiplex decoder control based on exclusively designed video core processor.
Features
| Standards Compliance - decoder only |
| ISO/IEC 14496-10 AVC BP@L4, MP@L4 ,HP@L4.1 |
| ISO/IEC 13818-2 MPEG-2 MP@HL |
| ISO/IEC 14496-2 MPEG-4 ASP (DivX) |
| SMPTE VC-1 SP, MP, AP@L3 |
| RV8/9/10 |
| JPEG |
Benefits
| Interface |
| Host interface: AMBA3 32-bit APB interface |
| External memory interface: AMBA3 64-bit AXI Interface or AMBA2 AHB interface |
| Customized interface for optimally designed bus multi-master environments can be available |
| Decoding tools |
| Support all features of the standards |
| Deblocking filter for post-processing |
| State-of-art error concealment strategy |
| Simultaneous multi-standard/multiple decoding is possible |
| Error resilience tools |
| Optional: Built-in rotation/mirroring function to remove redundant bus-loading: 90 x n degree rotation (n=0,1,2,3); Vertical/horizontal mirroring |
| Performance |
| HD(1920X1080) decoding @ 150MHz |
| Required host processor resource to run: less than 1 MIPS |
Deliverables
| RTL source code |
| IP integration guide & user guide |
| Test-bench |
| Evaluation Board |
| Part Number | BodaHx8 |
| Short description | MPEG-2 MP + H.264 HP + VC-1 AP + MPEG-4 ASP (DivX) + RV8/9/10 + JPEG codec (1920*1080*30) |
| Provider: | Chips&Media, Inc |
| Portability | FPGA |
| ASIC Target | TSMC@90um |
| FPGA Target | Xilinx Virtex 4 |
| Type | Soft |
| Compliant Standard | MPEG-2 MP@HL / MPEG-4 ASP (DivX) / H.264 HP@L4.1 / VC-1 AP@L3.0 / RV8/9/10 / JPEG codec (Full HD decoder) |
| Maturity | Very good |
| Availability | Oct, 2007 |
| TSMC Rating : | Verification: 0.09G (CLN90G) |
| FPGA Technology: | Xilinx: Virtex-4 LX |
| Bus Compliance : | AMBA AXI |
- Datasheet:
Related Links:
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Docs
How Do I Preserve MUX Structures in the Netlist?[from solvnet]
[I think it's very useful!]
How Do I Preserve MUX Structures in the Netlist?
Question:
I know that I can map the "full case" statements in RTL to MUX_OP synthetic components by using the "infer_mux" synthesis pragma or the "hdlin_infer_mux" global variable. However, in some cases I see that these MUX_OPs are inferred in the GTECH but mapped to non-MUX random logic gates in the library after compile or compile_ultra. How can I preserve these MUX structures even if the QOR is degraded with library MUX cells?
Answer:
If you want Design Compiler to preferentially map multiplexing logic to multiplexers or multiplexer trees in your technology library, you must infer MUX_OP cells. But it doesn't guarantee that the tool will use the MUX from the target library in the final implementation after compile or compile_ultra. Keep in mind that forcing MUXes might degrade the QOR of your design in some cases. So Design Compiler can change MUX_OPs to random logic based on the constraints. Starting from version Z-2007.03-SP3, you can use the set_size_only or set_map_only commands to set size_only or map_only attributes on the MUX_OP cells as follows: -Without size_only and map_only attributes, the MUX_OP synthetic cells are mapped to MUX cells if both area and delay are comparable to equivalent combinational random logic; otherwise combinational random logic is used. -With the map_only attribute, the MUX_OP is initially mapped to MUX cells, but are remapped to combinational random logic if delay can be improved; -With the size_only attribute, the MUX_OP is mapped to MUX cells. The size_only restricts optimization and can result in worse QOR. For example, you can set the attributes as one of the following: set_size_only [get_cells -hier * -filter "@ref_name =~ *MUX_OP*"] or set_map_only [get_cells -hier * -filter "@ref_name =~ *MUX_OP*"] Note: The "set_size_only" solution does not work in versions earlier to Z-2007.03-SP3. The "set_map_only" solution does not work in version earlier to Z-2007.03-SP2.
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Debussy Trace 2-D register array [tool usage tips]
In debussy/verdi v5.4 or below, the 2-D register array signal(speified in verilog-2001 syntax) can NOT be traced as usual.
We can add a parameter follow the command to make it support verilog-2001.
eg: verdi -2001 & or debussy -2001 &
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reduce run time for postgsim
When run the post gate level simulation, There usually need be a lone time(maybe several hours or several days for a huge design), so how to reduce the run time is a very useful job.
Firstly, we should analyze where the time consumed? As we know , the tool get the simulation result by calculating all the cell's logical value in the whole simulation process. And, all the process in the synchronous design is based the clock.
So, If we force the clock stop in the sub-design we need not care in the special pattern for the special function.There need be less time to calculate the cell's logical value . For example, we just need verify the video part, we do not need care the audio part, so we can force the clock for audio part on a stable state(gated clock).
It is a very useful method for the large design, specially the well-partitioned design.I use it to save almost the half hours.
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Some White Paper for Low-Power
Low-Power Resources
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Basic Low Power techniques to reduce Power[转]
From:http://socdesignsource.org/magicbluesmoke/?p=32
By gmaben
In the process of finding all the advanced techniques to reduce power, we tend to ignore the basic techniques available with the majority of EDA tools. Some of these techniques that are available today and can reduce power to a great extent are :-
(1) Clock gating
(2) Sizing
(3) Factoring
(4) Pin swapping
(5) Inversion Push
(6) Low Power Placement
(7) Register Clustering
(8) Low Power CTS to reduce power in the clock tree
(9) Multi-Vt Optimization to minimize usage of Low Vt cells
(10) Operand Isolation
(11) Data Gating
(12) Bubble Algorithm
These techniques can be enabled by turning on some switches/variables in the Implementation tools. Most of these techniques require representative vector-set. Identifying good representative vectors is a real challenge.
If the vectors are very difficult to access, the best bet would be to enable these techniques once your design meets the required timing/area goals.
We can definitely get an estimate on the average activity factor of various blocks of the design and use these factors to enable low power optimization. This approach can help us in saving power to quite an extent.
For example, I have seen in one of the recent activities, we were able to get around 15-20% power reduction just by enabling Low Power Placement.
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ECO小错
问题：
在定义wire的时候，信号名中带"\"，如wire \CNT[0] ;
不知道是公司的Naming Rule规定的还是Verilog语法规定，在此类信号名的前后必须有一个空格。
但我通过手工输入Command的方式产生的Netlist是不符合这规定的，因此很可能是公司Naming Rule定的。
结论：
在做ECO时手动修改的那部分Netlist一定得符合设计的Naming Rule，此类检查可以通过Debussy的语法检查发现。
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google技巧
在使用DC时，对于初学者来说，很难弄清楚那些具体的综合过程，不过我们可以通过command.log来了解它。
因此，就需要找一个比较好的脚本run过之后的command log来学习。
Google is very powerful！
对于文本文件，我们可以通过约束其扩展名，找到最精确的结果。
如我要找一个command.log的文件，我就可以在搜索栏输入synopsys command filetype:log
对于其他文本文件，也可以采取类似的方式来搜索。
同时，这也是一种不错的逆向学习方法，尤其对于这些EDA工具的学习。
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Tips
Linux 指令篇:档案目录管理--touch[转]
名称：touch
使用权限：所有使用者
使用方式：
touch [-acfm]
[-r reference-file] [--file=reference-file]
[-t MMDDhhmm[[CC]YY][.ss]]
[-d time] [--date=time] [--time={atime,access,use,mtime,modify}]
[--no-create] [--help] [--version]
file1 [file2 ...]
说明：
touch 指令改变档案的时间记录。 ls -l 可以显示档案的时间记录。
参数：
a 改变档案的读取时间记录。
m 改变档案的修改时间记录。
c 假如目的档案不存在，不会建立新的档案。与 --no-create 的效果一样。
f 不使用，是为了与其他 unix 系统的相容性而保留。
r 使用参考档的时间记录，与 --file 的效果一样。
d 设定时间与日期，可以使用各种不同的格式。
t 设定档案的时间记录，格式与 date 指令相同。
--no-create 不会建立新档案。
--help 列出指令格式。
--version 列出版本讯息。
范例：
最简单的使用方式，将档案的时候记录改为现在的时间。若档案不存在，系统会建立一个新的档案。
touch file
touch file1 file2
将 file 的时间记录改为 5 月 6 日 18 点 3 分，公元两千年。时间的格式可以参考 date 指令，至少需输入 MMDDHHmm ，就是月日时与分。
touch -c -t 05061803 file
touch -c -t 050618032000 file
将 file 的时间记录改变成与 referencefile 一样。
touch -r referencefile file
将 file 的时间记录改成 5 月 6 日 18 点 3 分，公元两千年。时间可以使用 am, pm 或是 24 小时的格式，日期可以使用其他格式如 6 May 2000 。
touch -d "6:03pm" file
touch -d "05/06/2000" file
touch -d "6:03pm 05/06/2000" file
touch 也可以制造一个空档(0 byte).例如DHCP Server所需的/etc/dhcpd.leases,dhcpd 必须要有这个档案才能运作正常.[root@/root]#touch /etc/dhcpd.leases[root@/root]#ls -l /etc/dhcpd.leases-rw-r--r-- 1 root root 0 Jul 3 05:50 /etc/dhcpd.leases
记得上一次重灌前把/etc下的设定档tar起来，重灌好之后把原有设定还原，却发现系统检查设定档的时间有问题，这个时候用
find /etc -name * -exec touch {};
就可以把设定档的时间更新到与现在一致了。
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Docs
Taiwan's IC Industry: Review of Q1 and Outlook for 2007
Taiwan's IC Industry: Review of Q1 and Outlook for 2007
<Just as a template of Industry Reports>
ITRI IEK-ITIS Project
1. 2007 Q1 Industry Overview
According to statistics released by the Industrial Economics and Knowledge Center (IEK) of the Industrial Technology Research Institute (ITRI), the production value of Taiwan's IC industry (including design, manufacturing, packaging and testing) was NT$339.5 billion in the first quarter of 2007. This represented a drop of 11.4% over the previous quarter (Q4 2006), but an increase of 10.6% relative to the first quarter of 2006 (the same period of the previous year). The design sector accounted for NT$84 billion (down 9.3% from Q4 2006, up 15.4% from Q1 2006), manufacturing for NT$182.5 billion (down 14.6% from Q4 2006, up 11.6% from Q1 2006), packaging for NT$50 billion (down 6.5% from Q4 2006, up 2.0% from Q1 2006), and testing for NT$23 billion (down 2.1% from Q4 2006, up 6.0% from Q1 2006). The following is a survey of the performance of Taiwan's IC design, manufacturing, packaging, and testing industries during the first quarter of 2007.
A. IC Design
In LCD-related IC design, revenue growth slowed due to the influence of flat screen product shipments during the first quarter; shipments of optical storage chipsets and DVD player chips remained steady. Shipments of low-grade mobile phones from China and India increased steadily, boosting mobile phone IC manufacturers' revenue. In the area of information product chipsets, Intel's and AMD's increasing focus on the embedded market, as well as NVIDIA's and ATI's reliance on their dominating graphics technology to lock up market share, has constricted the market for Taiwan's PC chipsets. In summary, the IC design sector had a production value of NT$84 billion during the first quarter of 2007; this figure was down 9.3% from the fourth quarter of 2006, but up 15.4% from the first quarter of 2006.
B. IC Manufacturing
Among Taiwan's two leading IC foundries, TSMC had revenue of NT$63.3 billion during the first quarter of 2007--a drop of 14% relative to the previous quarter--while UMC had revenue of NT$23 billion--which was similarly down by 12% over the previous quarter. These drops can mainly be attributed to customers' inventory adjustments. Spot prices of mainstream 512Mb DDR2 DRAM quickly fell from US$5 to below US$3 during the first quarter, and are now very close to manufacturers' production cost, which has also affected revenue performance. IC manufacturers had a production value of NT$182.5 billion during the first quarter of 2007; this represented a drop of 14.6% from the fourth quarter of 2006, but growth of 11.6 from the first quarter of that year.
C. IC Packaging and Testing
Seasonal factors and unfavorable market conditions caused the packaging and testing industry fall into a slump during the first quarter. Continued demand for packaging and testing of LCD driver ICs, memory cards, computer chipsets, chips for 3G mobile phones, and other communications and graphics chips will drive grow in the future, however. In summary, the IC packaging industry had production value of NT$50 billion during the first quarter of 2007, down 6.5% from the final quarter of 2006, but up 2.0% from the first quarter of that year. The testing industry had production value of NT$23 billion during the first quarter, which was down by 2.1% from the fourth quarter, but up 6.0% from the first quarter of 2006.
2. Outlook for the Second Quarter and all of 2007
In the design sector, demand will be driven by systems companies' continued introduction of popular new products like the Nintendo Wii, the Sony PS3 and the Apple iPhone. Taiwan's IC design industry is also expected to benefit from the ongoing effects of Microsoft's Vista, demand sparked by falling digital TV prices, and other business opportunities created by popular products. The IC industry is projected to have a production value of NT$87 billion during the second quarter, and achieve 3.6% growth relative to the first quarter. Production value for all of 2007 is projected to be NT$361.5 billion, which represents growth of 11.8% over 2006.
In the manufacturing sector, continued inventory adjustments by foundry customers will lead to a steadily increasing proportion of 90nm and 65nm advanced process product shipments. It is expected that Taiwan's IC foundries will have a second-quarter production value of NT$102.9 billion, a rise of 12.6% from the first quarter. The price of DRAM has fallen steadily, and is seen as bottoming out during Q2. This will drag down manufacturers' revenues and profits. The IC manufacturing industry as a whole is projected to have a production value of NT$172.9 billion during the second quarter, a 5.3% drop relative to Q1. The industry's production value for all of 2007 is projected to be NT$833.4 billion, growing 8.7% from 2006.
In the packaging and testing sector, demand for packaging and testing of chips used in PCs, mobile phones and digital consumer electronics products and peripherals may grow. Microsoft's Vista is expected to sustain growth in PC-related markets. The 2008 Beijing Olympics should also provide opportunities for the consumer electronics industry. Demand for mid-range and low end products in India and other emerging markets will continue. The production value of the packaging and testing industry is expected to reach NT$76.5 billion in the second quarter of 2007, an increase of 4.8% over the first quarter. Production value for all of 2007 is projected to be NT$341.3 billion, an increase of 12.6% relative to 2006.
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Synopsys synthesis tutorial
some tutorials from the synopsys install directoy,maybe it's too old for the latest tool.
点击下载, Click for Download
keywords:Design compiler ,Power Compiler,Scan chain insertion,script,synthesis example,DC脚本,综合实例
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EFA Flex License Generator 0.4beta
A very power Flex License Generator: (点击下载)(Click to Download)
Related link:
http://www.woodmann.net/crackz/Flexlm.htm
License For The vendor list below:
Actel
AgilentADS_1.5
Aldec Active HDL
Aldec Active HDL70
Aldec RIVIERA
Allegro14_Cdslmd
Allegro14_PSLD
Altera
AnalyticalGraphics_STK42
AnsoftMaxWell
AnsoftSerenade_8.5
Aplac76
Asset
Atlass
Avanti
AvantiCorp
Cadence Design Systems
Cadence Design Systems_6
Cadence Design Systems_7
Cadence Design Systems_71
Cadence
CadencePSD_14.2
Concept_GateVision
CST_MicroWave_Studio_3.2
Dolphin-Smash
FPGACompilerII_3.6
GerbTool_10
HyperLynx_6.0
Laker LayoutEditor
Laker
Laker1
Laker_Any
LSI-Logic
Magma
Mars_Synplify
Micromagic
modeltech
ModelTech71
ModeltechBundle
MWO2001
NovasDebussy_5
NovasLaker
novas_50v16
Simplex
SonetLite
SynaptiCad_7.5
Synopsys
Synplicity
Synplicity_6.2
Synplify Synplicity
TransEDA
TranslogicHDLEntry_5
verisity
Veritools
Verplex
Viewlogic
VirageLogic
X-Tek
4
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EDA,
Software
关于状态机写法的一点看法 FSM Finite State Machine
关于以下两种状态机，说点自己的见解。
1. reg control_signal;
always @(c_s or other_sensitive_variable)
begin
control_signal = 1'b0;
......
case(c_s)
state0:
state1:
begin
control_signal = 1'b1;
if(sensitive_variable1)
n_s = state2;
end
...
endcase
end
always @(clk or rstj)
if(!rstj)
c_s <= case_init ;
else
c_s <= n_s;
2. wire control_signal = c_s == state2;
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Analog Design 100 tips[转]
1/ Capacitors and resistors have parasitic inductance, about 0.4nH for surface mount and 4nH for a leaded component.
2/ If you don"t want a high bandwidth transistor to oscillate place lossy components in at least 2 of the 3 leads. Ferrite beads work well.
3/ When taking DC measurements in a circuit and they don"t make sense, suspect that something is oscillating.
4/ Opamps will often oscillate when driving capacitive loads.
5/ The base-emitter voltage Vbe of a small signal transistor is about 0.65v and drops about 2mV/deg C. Vbe goes down with increasing temp.
6/ Multiply 0.13nV by the square root of the ohmic value of a resistor to find the noise in a 1Hz bandwidth. Then multiply by the square root of the BW in Hz gives the total noise voltage.
7/ Johnson noise current goes down with a increase in resistance.
8/ The impedance looking into the emitter of a transistor at room temp is 26Ohm/Ie in mA
9/ All amplifiers are differential in that they are referenced to ground somewhere.
10/ Typical metal film resistor has a temp coef of about 100 ppm/deg C
11/ The input noise voltage of a quiet op amp is 1nv/sqrt(Hz) but there are plenty available with 20nV/sqrt(Hz). Op amps with bipolar front-ends have lower voltage noise and higher current noise than those with FET front-ends
12/ Using an LC circuit as a power supply filter can actually multiply the power supply noise at the filter"s resonant frequency. Use inductor with low Q to overcome this.
13/ Use comparators for comparing and op amps for amplifying and don"t even think of mixing the two.
14/ Ceramic caps with any other dielectric other than NPO should only be used for bypass applications.
15/ An N-channel enhancement-mode FET needs +ve voltage on the gate-source to conduct form drain-source.
16/ Small signal JFETS work very well as low-leakage diodes by connecting drain & source together in log current-to-voltage converters and low leakage input protection. Small signal bipolars with b-c tied together will also make nice low-leakage diodes.
17/ With low pass filter use Bessel for least amount of overshoot in the time domain, and Cauer (or elliptic) for fastest rolloff in the freq domain.
18/ dB is always 10 times the log of the ratio of 2 powers.
19/ At low frequencies, the current in the collector of a transistor is in phase with the applied current at the base. At high frequencies the current at the collector lags by 90deg. You must appreciate this simple fact to understand high frequency oscillators.
20/ The most common glass-epoxy PCB material (FR4) has a dielectric constant of about 4.3 To make a trace with a characteristic impedance of 100 Ohm, use a trace thickness of about 0.4 times the thickness of the board with a ground plane on the opposite side. For a 50Ohm trace make it 2 times the thickness.
21/ If you need a programmable dynamic current source, find out about operational transconductance amps. Most of the problem is figuring out when you need a programmable dynamic current source.
22/ A CMOS output with an emitter follower can drive a 5V relay nicely as the relays normally have a must-make spec of 3.5V. This saves power and require no flyback components.
23/ Typical thermocouple potential is 30uV/degC. Route signals differentially, along the same path, avoid temp gradients. DPDT latching relays won"t heat up when multiplexing these signals.
24/ You SHOULD be bothered by a design that looks messy, cluttered or indirect. This uncomfortable feeling is one of the few indications that there"s a better way.
25/ Avoid drawing any current from the wiper of a potentiometer. The resistance of the wiper contact will cause problems (local heating, noise offsets etc.)
26/ Most digital phase detectors have a deadband where the analog output does not change over the small range where the 2 inputs are coincident. This often-ignored fact has helped to create some very noisy PLL"s (Use a high val bleeding resistor to always ensure current flow in the deadband)
27/ The phase noise of a phase-locked VCO will be at least 6dB worse than the phase noise of the divided reference for each octave between the comparison frequency and the VCO output frequency. Avoid low-comparison frequencies.
28/ You can almost always determine the leads of a bipolar transistor with an ohm meter. b-e and b-c junctions will measure like a diode with the b-c junction reading slightly lower than the b-e junction when forward biased.
29/ For low distortion, the drains (or collectors) of a differential amp"s front-end should be bootstrapped to the source (or emitter) so that the voltages on the part are not modulated by the input signal.
30/ If your design uses a $3 op amp, and you will be making a thousand of them, you have just spend $3000. Are you smart enough to figure out how to use a $.30 op amp instead?
31/ The Q of an LC tank circuit is dominated by the losses in the inductor in terms of series R. Q=omega.L/R
32/ Leakage current doubles for every 10degC increase in temp.
33/ When inputs to most JFET op amps exceed the common-mode range for the part, the output may reverse polarity. This artifact will haunt the designers of these parts for the rest of their lives, as it should!
34/ Understand the difference between "make-before-break" and "break-before-make" when you specify switches.
35/ 3 Terminal voltage regulators in the TO-220 packages are wonderful parts. They are cheap, rugged, thermally protected and very versatile. Use them virtually any place where you need a protected power transistor. They also make nice AM power-modulators.
36/ Use step recovery diode where you need fast edges under 100pS (hot-carrier is even faster)
37/ The old 723 regulator is still one of the lowest noise regulators around! (2.5uVrms 100Hz-10k)
38/ You can make a very simple oscillator with one diac, cap and a resistor.
39/ NPN transistors are normally superior to their PNP counterpart in performance.
40/ Typical spec in some databooks should read "Seen it once". Always work with the worst spec of the part when doing a design.
41/ Don"t just copy circuits from application notes without understanding completely how it operates, and the reason for the choice of values.
42/ Dealing with crystals, make sure you understand the difference between series and parallel resonant. In a circuit, crystal frequency can generally be slightly lowered by placing a inductor in series and increased by a capacitor in series.
43/ Power MOSFETS on-resistance will have a -ve temp coef and not +ve at low current levels. This is important to remember when paralleling devices.
44/ Lowest noise figure of a RF transistor is not normally where the input is perfectly matched.
45/ Many un-stable RF devices can be made stable by loading the input or the output by a simple resistor, either in series or parallel.
46/ You trade gain for bandwidth.
47/ Push-pull power invertors using bipolars are risky and can saturate the core because of hysteresis stepping (use power fets)
48/ The Al value of a core will increase up to 50% or more under current transients.
49/ Be aware of leakage inductance when switching. V=L(dI/dt)
50/ The harder you turn-on a power transistor, the longer it will take to turn off.( the part where you burn the joules in the device)
51/ Always remember the Miller guy.
52/ In fault-finding a circuit, don"t overlook the obvious. (is there power?)
53/ What is a ground loop, and how to avoid it.
54/ 120 is a better number than 240 when using LM3XX type adjustable regulators.
55/ The lower comparator in the old 555 may have quite a long storage time.
56/ ZERO-ESR caps may do more harm than good.
57/ A correctly configured audio power amplifier will give more distortion in Class-AB, not less, because of the abrupt gain changes inherent in switching from A to B every cycle.
58/ Be a STAR when it comes to ground matters.
59/ Know when you need to use a Zobel network.
60/ Use current mirrors and mirror your current.
61/ Heatsink eff decreases with height above sealevel.
62/ A matt-black heatsink is much better than a shiny one.
63/ Ignoring secondary breakdown can be costly.
64/ Understand fuses and fuse ratings, fast and slow. Do you know when to use a semiconductor-fuse?
65/ Charge balancing resistors are a must when stacking serie-parallel high voltage capacitor banks.
66/ You must understand DC-restoration otherwise you will have a hard time designing Z-modulation in CRT circuits.
67/ Display 6 vert div low freq on a scope, increase the freq (make sure the source is constant amplitude) until display drops to 4.2 div. That is the true 3dB BW of the scope. (scope-source impedance should be matched)
68/ Doing a measurement with your DMM in the ACV position on your DC circuit will give a quick indication of any excess ripple on the supply when you don"t have a scope at hand.
69/ Dly timebase on a scope is very useful once you figured out when, why and how to use it.
70/ Know what to expect before you measure, otherwise any measurement is meaningless.
71/ Op amps. Output will swing in the direction that will force the inv-input level to try come closer to the non-inv input level.
72/ Understand virtual ground, slew-rate, CMRR and PSRR. (CMRR decrease with increase in freq)
73/ Making measurements near a spec-analalyzer"s noise floor will give 3dB errors.
74/ Understand the phase-noise limitations of the analyzer when making such measurements on oscillators.
75/ In a LC oscillator add some C with -ve temp coef to cancel the +ve temp coef of the L for min drift with temp.
76/ Less drift will result from making C with a few parallel caps, to reduce the heating effect of the oscillating current when spread out over a larger plate area.
77/ You will get more tuning range with the same LC combination in a Clapp than in a Colpitts circuit.
78/ High-Q tuned LC filters will have more insertion loss.
79/ Williams"s Rule (Guru at Linear Tech) for precision op amp circuits: " Always invert (except when you can"t)"
80/ Cuk is not a kind of locomotive.
81/ If you don"t know how to make a design better, find out what makes it worse.
82/ Sometimes you know just enough to be dangerous.
83/ Impedance will reflect back as the square of the turns ratio.
84/ If you could design a component with the characteristics of a finger it could cure many design problems and you will be rich.
85/ Get nervous when the customer you are trying to help doesn"t even have a scope.
86/ Specs quoted by reps always exceed those by Engineering.
87/ A bad (Engineer) workman always blames his tools.
88/ Don"t believe everything that a SPICE program spits out.
89/ It is easy to get the color code of a 1kOhm and 12Ohm resistor mixed up when you are in a hurry.
90/ I bet one could write a thesis about the ability of probes to get tangled-up on a bench.
91/ DMM can upset sensitive circuits from noise generated inside it.
92/ When probing directly on a crystal of a uP, use 10kOhm or so resistor in series with the probe tip to prevent loading from stopping the osc.
93/ It is easier to see what is happening on the ports using a scope when you trigger one chan against the cpu clock.
94/ National once made a bad op amp many years ago that some Engineers referred to it as "Jelly Beans"
95/ The moment you can start to notice distortion on an oscilloscope it is already way past being acceptable.
96/ Be big enough to say "I don"t know", people will respect you more.
97/ The best designer is often working in the marketing department.
98/ Some remarkable discoveries/inventions were made by people that knew very little about the subject. Don"t fall into a groove in you thinking process.
99/ The Peter-Principle : Everybody will be promoted up to his own level of incompetence. http://pespmc1.vub.ac.be/PETERPR.html
100/ END-Enjoy
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