[I think it's very useful!]
How Do I Preserve MUX Structures in the Netlist?
Question:
I know that I can map the "full case" statements in RTL to MUX_OP synthetic components by using the "infer_mux" synthesis pragma or the "hdlin_infer_mux" global variable. However, in some cases I see that these MUX_OPs are inferred in the GTECH but mapped to non-MUX random logic gates in the library after compile or compile_ultra. How can I preserve these MUX structures even if the QOR is degraded with library MUX cells?
Answer:
If you want Design Compiler to preferentially map multiplexing logic to multiplexers or multiplexer trees in your technology library, you must infer MUX_OP cells. But it doesn't guarantee that the tool will use the MUX from the target library in the final implementation after compile or compile_ultra. Keep in mind that forcing MUXes might degrade the QOR of your design in some cases. So Design Compiler can change MUX_OPs to random logic based on the constraints. Starting from version Z-2007.03-SP3, you can use the set_size_only or set_map_only commands to set size_only or map_only attributes on the MUX_OP cells as follows: -Without size_only and map_only attributes, the MUX_OP synthetic cells are mapped to MUX cells if both area and delay are comparable to equivalent combinational random logic; otherwise combinational random logic is used. -With the map_only attribute, the MUX_OP is initially mapped to MUX cells, but are remapped to combinational random logic if delay can be improved; -With the size_only attribute, the MUX_OP is mapped to MUX cells. The size_only restricts optimization and can result in worse QOR. For example, you can set the attributes as one of the following: set_size_only [get_cells -hier * -filter "@ref_name =~ *MUX_OP*"] or set_map_only [get_cells -hier * -filter "@ref_name =~ *MUX_OP*"] Note: The "set_size_only" solution does not work in versions earlier to Z-2007.03-SP3. The "set_map_only" solution does not work in version earlier to Z-2007.03-SP2.
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