reduce run time for postgsim

When run the post gate level simulation, There usually need be a lone time(maybe several hours or several days for a huge design), so how to reduce the run time is a very useful job.
Firstly, we should analyze where the time consumed? As we know , the tool get the simulation result by calculating all the cell's logical value in the whole simulation process. And, all the process in the synchronous design is based the clock.
So, If we force the clock stop in the sub-design we need not care in the special pattern for the special function.There need be less time to calculate the cell's logical value . For example, we just need verify the video part, we do not need care the audio part, so we can force the clock for audio part on a stable state(gated clock).
It is a very useful method for the large design, specially the well-partitioned design.I use it to save almost the half hours.