Showing posts with label fpga. Show all posts
Showing posts with label fpga. Show all posts

Nov 20, 2007

[转]What is the difference between FPGA and ASIC?

  • This question is very popular in VLSI fresher interviews. It looks simple but a deeper insight into the subject reveals the fact that there are lot of thinks to be understood !! So here is the answer.
FPGA vs. ASIC
  • Difference between ASICs and FPGAs mainly depends on costs, tool availability, performance and design flexibility. They have their own pros and cons but it is designers responsibility to find the advantages of the each and use either FPGA or ASIC for the product. However, recent developments in the FPGA domain are narrowing down the benefits of the ASICs.
FPGA
  • Field Programable Gate Arrays
FPGA Design Advantages
  • Faster time-to-market: No layout, masks or other manufacturing steps are needed for FPGA design. Readymade FPGA is available and burn your HDL code to FPGA ! Done !!
  • No NRE (Non Recurring Expenses): This cost is typically associated with an ASIC design. For FPGA this is not there. FPGA tools are cheap. (sometimes its free ! You need to buy FPGA.... thats all !). ASIC youpay huge NRE and tools are expensive. I would say "very expensive"...Its in crores....!!
  • Simpler design cycle: This is due to software that handles much of the routing, placement, and timing. Manual intervention is less.The FPGA design flow eliminates the complex and time-consuming floorplanning, place and route, timing analysis.
  • More predictable project cycle: The FPGA design flow eliminates potential re-spins, wafer capacities, etc of the project since the design logic is already synthesized and verified in FPGA device.
  • Field Reprogramability: A new bitstream ( i.e. your program) can be uploaded remotely, instantly. FPGA can be reprogrammed in a snap while an ASIC can take $50,000 and more than 4-6 weeks to make the same changes. FPGA costs start from a couple of dollars to several hundreds or more depending on the hardware features.
  • Reusability: Reusability of FPGA is the main advantage. Prototype of the design can be implemented on FPGA which could be verified for almost accurate results so that it can be implemented on an ASIC. Ifdesign has faults change the HDL code, generate bit stream, program to FPGA and test again.Modern FPGAs are reconfigurable both partially and dynamically.
  • FPGAs are good for prototyping and limited production.If you are going to make 100-200 boards it isn't worth to make an ASIC.
  • Generally FPGAs are used for lower speed, lower complexity and lower volume designs.But today's FPGAs even run at 500 MHz with superior performance. With unprecedented logic density increases and a host of other features, such as embedded processors, DSP blocks, clocking, and high-speed serial at ever lower price, FPGAs are suitable for almost any type of design.
  • Unlike ASICs, FPGA's have special hardwares such as Block-RAM, DCM modules, MACs, memories and highspeed I/O, embedded CPU etc inbuilt, which can be used to get better performace. Modern FPGAs are packed with features. Advanced FPGAs usually come with phase-locked loops, low-voltage differential signal, clock data recovery, more internal routing, high speed, hardware multipliers for DSPs, memory,programmable I/O, IP cores and microprocessor cores. Remember Power PC (hardcore) and Microblaze (softcore) in Xilinx and ARM (hardcore) and Nios(softcore) in Altera. There are FPGAs available now with built in ADC ! Using all these features designers can build a system on a chip. Now, dou yo really need an ASIC ?
  • FPGA sythesis is much more easier than ASIC.
  • In FPGA you need not do floor-planning, tool can do it efficiently. In ASIC you have do it.
FPGA Design Disadvantages
  • Powe consumption in FPGA is more. You don't have any control over the power optimization. This is where ASIC wins the race !
  • You have to use the resources available in the FPGA. Thus FPGA limits the design size.
  • Good for low quantity production. As quantity increases cost per product increases compared to the ASIC implementation.
ASIC
  • Application Specific Intergrated Circiut
ASIC Design Advantages
  • Cost....cost....cost....Lower unit costs: For very high volume designs costs comes out to be very less. Larger volumes of ASIC design proves to be cheaper than implementing design using FPGA.
  • Speed...speed...speed....ASICs are faster than FPGA: ASIC gives design flexibility. This gives enoromous opportunity for speed optimizations.
  • Low power....Low power....Low power: ASIC can be optimized for required low power. There are several low power techniques such as power gating, clock gating, multi vt cell libraries, pipelining etc are available to achieve the power target. This is where FPGA fails badly !!! Can you think of a cell phone which has to be charged for every call.....never.....low power ASICs helps battery live longer life !!
  • In ASIC you can implement analog circuit, mixed signal designs. This is generally not possible in FPGA.
  • In ASIC DFT (Design For Test) is inserted. In FPGA DFT is not carried out (rather for FPGA no need of DFT !) .
ASIC Design Diadvantages
  • Time-to-market: Some large ASICs can take a year or more to design. A good way to shorten development time is to make prototypes using FPGAs and then switch to an ASIC.
  • Design Issues: In ASIC you should take care of DFM issues, Signal Integrity isuues and many more. In FPGA you don't have all these because ASIC designer takes care of all these. ( Don't forget FPGA isan IC and designed by ASIC design enginner !!)
  • Expensive Tools: ASIC design tools are very much expensive. You spend a huge amount of NRE.
Structured ASICS
  • Structured ASICs have the bottom metal layers fixed and only the top layers can be designed by the customer.
  • Structured ASICs are custom devices that approach the performance of today's Standard Cell ASIC while dramatically simplifying the design complexity.
  • Structured ASICs offer designers a set of devices with specific, customizable metal layers along with predefined metal layers, which can contain the underlying pattern of logic cells, memory, and I/O.
FPGA vs. ASIC Design Flow Comparison Other links

Nov 6, 2007

A good blog for fpga

FPGA design from scratch

http://svenand.blogdrive.com/

ISE8.2 sn 序列号 serial number ID

ISE 8.2: 5876-1279-7287-2760

Xilinx FPGA全局时钟和第二全局时钟资源的使用方法[转贴]

目前,大型设计一般推荐使用同步时序电路。同步时序电路基于时钟触发沿设计,对时钟的周期、占空比、延时和抖动提出了更高的要求。为了满足同步时序设计的要求,一般在FPGA设计中采用全局时钟资源驱动设计的主时钟,以达到最低的时钟抖动和延迟。 FPGA全局时钟资源一般使用全铜层工艺实现,并设计了专用时钟缓冲与驱动结构,从而使全局时钟到达芯片内部的所有可配置单元(CLB)、I/O单元(IOB)和选择性块RAM(Block Select RAM)的时延和抖动都为最小。为了适应复杂设计的需要,Xilinx的FPGA中集成的专用时钟资源与数字延迟锁相环(DLL)的数目不断增加,最新的Virtex II器件最多可以提供16个全局时钟输入端口和8个数字时钟管理模块(DCM)。 与全局时钟资源相关的原语常用的与全局时钟资源相关的Xilinx器件原语包括:IBUFG、IBUFGDS、BUFG、BUFGP、BUFGCE、BUFGMUX、BUFGDLL和DCM等,如图1所示。
1. IBUFG即输入全局缓冲,是与专用全局时钟输入管脚相连接的首级全局缓冲。所有从全局时钟管脚输入的信号必须经过IBUF元,否则在布局布线时会报错。IBUFG支持AGP、CTT、GTL、GTLP、HSTL、LVCMOS、LVDCI、LVDS、LVPECL、LVTTL、PCI、PCIX和SSTL等多种格式的IO标准。
2. IBUFGDS是IBUFG的差分形式,当信号从一对差分全局时钟管脚输入时,必须使用IBUFGDS作为全局时钟输入缓冲。IBUFG支持BLVDS、LDT、LVDSEXT、LVDS、LVPECL和ULVDS等多种格式的IO标准。
3. BUFG是全局缓冲,它的输入是IBUFG的输出,BUFG的输出到达FPGA内部的IOB、CLB、选择性块RAM的时钟延迟和抖动最小。
4. BUFGCE是带有时钟使能端的全局缓冲。它有一个输入I、一个使能端CE和一个输出端O。只有当BUFGCE的使能端CE有效(高电平)时,BUFGCE才有输出。
5. BUFGMUX是全局时钟选择缓冲,它有I0和I1两个输入,一个控制端S,一个输出端O。当S为低电平时输出时钟为I0,反之为I1。需要指出的是BUFGMUX的应用十分灵活,I0和I1两个输入时钟甚至可以为异步关系。
6. BUFGP相当于IBUG加上BUFG。
7. BUFGDLL是全局缓冲延迟锁相环,相当于BUFG与DLL的结合。BUFGDLL在早期设计中经常使用,用以完成全局时钟的同步和驱动等功能。随着数字时钟管理单元(DCM)的日益完善,目前BUFGDLL的应用已经逐渐被DCM所取代。 (Q08. DCM即数字时钟管理单元,主要完成时钟的同步、移相、分频、倍频和去抖动等。DCM与全局时钟有着密不可分的联系,为了达到最小的延迟和抖动,几乎所有的DCM应用都要使用全局缓冲资源。DCM可以用Xilinx ISE软件中的Architecture Wizard直接生成。
全局时钟资源的使用方法 全局时钟资源的使用方法(五种) 1:IBUFG + BUFG的使用方法: IBUFG后面连接BUFG的方法是最基本的全局时钟资源使用方法,由于IBUFG组合BUFG相当于BUFGP,所以在这种使用方法也称为BUFGP方法。
2. IBUFGDS + BUFG的使用方法: (C8t0a8Uu0当输入时钟信号为差分信号时,需要使用IBUFGDS代替IBUFG。
3. IBUFG + DCM + BUFG的使用方法: 这种使用方法最灵活,对全局时钟的控制更加有效。通过DCM模块不仅仅能对时钟进行同步、移相、分频和倍频等变换,而且可以使全局时钟的输出达到无抖动延迟。
4. Logic + BUFG的使用方法: BUFG不但可以驱动IBUFG的输出,还可以驱动其它普通信号的输出。当某个信号(时钟、使能、快速路径)的扇出非常大,并且要求抖动延迟最小时,可以使用BUFG驱动该信号,使该信号利用全局时钟资源。但需要注意的是,普通IO的输入或普通片内信号进入全局时钟布线层需要一个固有的延时,一般在10ns左右,即普通IO和普通片内信号从输入到BUFG输出有一个约10ns左右的固有延时,但是BUFG的输出到片内所有单元(IOB、CLB、选择性块RAM)的延时可以忽略不计为“0”ns。
5. Logic + DCM + BUFG的使用方法:DCM同样也可以控制并变换普通时钟信号,即DCM的输入也可以是普通片内信号。使用全局时钟资源的注意事项 全局时钟资源必须满足的重要原则是:使用IBUFG或IBUFGDS的充分必要条件是信号从专用全局时钟管脚输入。换言之,当某个信号从全局时钟管脚输入,不论它是否为时钟信号,都必须使用IBUFG或IBUFGDS;如果对某个信号使用了IBUFG或IBUFGDS硬件原语,则这个信号必定是从全局时钟管脚输入的。如果违反了这条原则,那么在布局布线时会报错。这条规则的使用是由FPGA的内部结构决定的:IBUFG和IBUFGDS的输入端仅仅与芯片的专用全局时钟输入管脚有物理连接,与普通IO和其它内部CLB等没有物理连接。 另外,由于BUFGP相当于IBUFG和BUFG的组合,所以BUFGP的使用也必须遵循上述的原则。
全局时钟资源的例化方法 全局时钟资源的例化方法大致可分为两种: 一是在程序中直接例化全局时钟资源; 二是通过综合阶段约束或者实现阶段约束实现对全局时钟资源的使用;第一种方法比较简单,用户只需按照前面讲述的5种全局时钟资源的基本使用方法编写代码或者绘制原理图即可。
第二方法是通过综合阶段约束或实现阶段的约束完成对全局时钟资源的调用,这种方法根据综合工具和布局布线工具的不同而异。

ISE批处理方式

说明:
1.此文件用于将edf网表文件到FPGA的bit文件产生;
2.将注释里面的内容复制到一个bat文件中,保存即可;
3.可用于固化设计环境或者计划任务等。

/**************************/
path ISE_Install_Path/bin/nt
ngdbuild -intstyle xflow -verbose -dd ./_ngo -uc *.ucf -sd /MACRO_PATH -p xc4vlx200-ff1513-10 design_name.edf design_name.ngdmap -intstyle xflow -p xc4vlx200-ff1513-10 -cm balance -pr b -k 4 -c 99 -tx off -o design_name_map.ncd design_name.ngd design_name.pcf par -w -intstyle xflow -ol high -t 1 design_name_map.ncd design_nameip.ncd design_name.pcftrce -intstyle xflow -e 3 -l 3 -xml design_name design_name.ncd -o design_name.twr design_name.pcfbitgen -w design_name.ncd
/**************************/

注释:
line1:path ISE 命令文件的路径,以确保下面的命令能被windows正常调用,会batch的人都知道;
line2:将edf转化成ISE能识别的ndg格式,读取ucf文件;
line3:map过程,将电路网表映射到FPGA内部逻辑单元的网表,产生.ncd和pcf文件;
line4:par,Place and Route,布局布线,使用到map产生的ncd和pcf文件;
line5:trce,产生时序报告
line6:bitgen,产生bit文件

详细命令参数可参阅ISE的UserGuide。

在Linux或者Unix下面运行时候除第一行有差别之外,其他等同。

FPGA入门学习方法

a)首先学习FPGA的datasheet和userguide,一定要仔细看下来,第一次看也许会有点难度,但坚持下来好处多多。
b)原理图学习,一般学习者手上都有开发板,可以拿现成的板子来学习。一般来说,FPGA板级主要分三部分,配置(JTAG or Parallel,.etc)、时钟、IO。配置部分就是TCLK,TRST,TDI,TDO,TMS和Ground6根线(JTAG方式,Xilinx),时钟对于一般初学者使用的开发板来说才一到两个,一般来说就是接FPGA的GCLK(全局时钟资源)输入。假如时钟输入不是接的全局时钟管脚,在设计时需特别处理。IO部分的话主要就是参考电压,即Ref**的管脚,该部分涉及到各Bank的电平标准设置,对于初学者,且无特殊使用时可以暂先不管。
c)工具的学习。强烈建议看工具的帮助文件,Tutorial,Manual,User Guide等,不要怕太多,英文看不懂,只要坚持过一次,以后就会轻松很多。
d)设计流程。从Coding ->Simulation ->Synthesis ->Implement ->Configuration ->Download。用于初学的设计要简单,且能在开发板上看到效果,如设计一个计数器,让一个LED闪烁。采用HDL的话需要注意可综合的问题。
e)报告分析。这点很关键,而且往往被初学者忽视。一般来说那些报告文件都是文本格式,虽然后缀名不是txt,但用文本编辑器都是可以打开的,如UltraEdit。当然,直接用工具打开是肯定可以的。报告中不懂的东西可以从软件的Manual或者Userguide中间能够找到,找不到的话google也可以。说到google,顺便提两句搜索的技巧,如果想搜索技术方面的东西的话,最好是google,关键字最好是英文的,而且最好不要是很通俗的,如果你要搜索的关键字是很通俗的话,建议再加一个该方面常用的专业词汇。
f)问题解决方法。关于碰到问题该怎么办,很多人第一选择可能就是去论坛发帖或者google。本人是不太喜欢去论坛发帖求教,一是实时性太差,往往等好几天还不一定有人帮你回答,二是论坛中的高手往往是喜欢交流,而不是一味地教导别人。所以,要在论坛发问,最起码你要具备交流的资格,能很清楚地描述你的问题,能说清楚你对于此问题采取过的努力及取得的成效。最忌的是漫无边际地提问,如"我正在学习FPGA,请高手教我该怎么做?"。Google答案我认为是一种比较快捷的手段,也是我平时学习工作采取最多的方法之一。不过正统的办法是自己思考问题,从理论上去找到解决该问题的办法。这点往往也是初学者所缺乏的。