async fifo design

Key points:
1. fifo body: dual ports sram or registers array
2. read and write address for sram
3. empty and full flag for the fifo body, it's the most important, and there are two methods presented in the reference paper.
4. almost empty or almost full flag, if needed
5. fifo content depth or fifo space depth, if needed
6. some special case for the special application, eg.  the predicable  r/w clock frequence ratio.

Reference paper:
 http://www.sunburst-design.com/papers/