Query Yourself before Architecting a Chip

[From:http://www.vlsichipdesign.com/askyourselfarchitect.html]
This article assuming you are an Architect and What all questions will come to your thought process before Architecting and making the Chip as a first-pass success. Chip Design is an Integration Challenge.

1. What is the targetted market for this Chip.
2. What are the competitor's to this Chip and Market Requirement and ROI
3. What is the Fabrication Unit the Chip is targetted for?
4. What is the Success rate and Yield numbers achieved in the Fabrication Unit
5. What is the technology Process targetted for
6. What is the correlation of the library models w.r.t. Silicon
7. What are the various Protocols the Chip is going to address
8. Hardware & Software Parti-tioning.
9. What is the processor/micro-controller suitable for this application.
10. What is the bus-architecture targetted
11. What is the performance targets for this bus architecture
12. What are the various Interfaces the Chip is having
13. Is the design going to be in single Vt or with Multi-Vt design
14. Is using Embedded macro's right choice or Memory Macros
15. What are the IP's are going to be Re-usued
16. What are the IP's going to Hard-macro's
17. What is the Verification Status and corner-case coverage of the I.P's
18. What is the Die-size targetted/Estimated for the Chip
19. What is the Power targets
20. Is Power Management Unit a requirement in the chip to reduce Dynamic power
21. What are the mechanisms followed to reduce the leakage power
22. Is Module enables/clock-gating a part of the Methodology
23. Is resets going to synchronous or asynchronous
24. What are the various Synchronous Mechanisms for data-transfer's
25. How many clock-domains required for the Chip
26. How many PLL's are required or single PLL sufficient for all the clocks required
27. What is the thought process behind PAD's Is LVTTL/SSTL pads
28. Is the package going to wire-bond or Flip-chip
29. Methodology for Optimal Power-grid design
30. What are the noise reducing Mechanism's in case of analog integration
31. Is there any requirement of speed monitor's or process checking blocks
32. What is the type of fuses used laser fuse or efuses
33. Is there any requirement of Fib Cells in the Design
34. What are the mechanism's used to handle ESD
35. what is the reliability target of the Chip and how it is addressed
36. What are the Mechanisms used for Yield improvement
37. Is the chip tested at at-speed test
38. How much Memory-map is allocated for the IP's
39. What is the metric for spare-gates in the Chip for ECO's
40. Is repairable memories required
41. What is the tester targetted and the requirement to the Chip in terms of Scan-chain
42. Is test-vector compression mechanism's a requirement
43. What is the PLL performance in terms of Jitter
44. What is the Interrupt handling mechanism with in the Chip.
45. What is the ROM-Code for the Chip.
46. What is the Chip utilization targets
47. Will the chip be routable or any requirement for special libraries with different routing tracks.
48. What is the Methodology for tools and versions
49. What is the Version control mechanism planned for data handling across multi Geographical Environments.
50. What is the signoff criteria for the Chip
51. What is the frequency targets for the Chip.
52. Is there room for further revisions of the Chip.
53. If the Chip has DDR/SDR interface is there any requirement for DLL.
54. What are the limitations of the Tools interms of Complexity/run-times/turn-around times/Computation Power requirements.
55. What is the Mechanisms/Steps taken for the various Variabilities in the Chip IR drop/Power ground noise/inductance effects/EMI noise/Package noise/Crosstalk noise/Simultaneous Switching noise/Channel length variation/On chip Variation/Inter die variations/Intra die Process variations.