On Chip Variations or inter-die variations could be caused due to :
• IR drop
• Vt variations
• Channel length variation
So the normal flow of qualifying the Timing with plain worst and best corners is no more enough.
Performing On-Chip Variation Analysis[From PrimeTime UG]
To perform on-chip variation analysis, use the set_operating_conditions command.
Because on-chip variations consider that cells and nets can operate at slightly different operating conditions, you must consider a minimum value and a maximum value for each delay of the design.Specify two operating conditions to represent the lower and upper bounds of the operating condition for on-chip variation, keeping the following guidelines in mind.
• Each delay of the design has an uncertainty bounded by the minimum value (computed for the minimum operating condition) and maximum value (computed for the maximum operating condition).
• Minimum paths are computed using the delay of the minimum operating condition.
• Maximum paths are computed using the delay of the maximum operating condition.
To perform on-chip variation analysis, use the set_operating_conditions command.
Because on-chip variations consider that cells and nets can operate at slightly different operating conditions, you must consider a minimum value and a maximum value for each delay of the design.Specify two operating conditions to represent the lower and upper bounds of the operating condition for on-chip variation, keeping the following guidelines in mind.
• Each delay of the design has an uncertainty bounded by the minimum value (computed for the minimum operating condition) and maximum value (computed for the maximum operating condition).
• Minimum paths are computed using the delay of the minimum operating condition.
• Maximum paths are computed using the delay of the maximum operating condition.
Example 1
This command sequence performs timing analysis for on-chip variation 20 percent below the worst-case commercial (WCCOM)
operating condition. It also performs clock reconvergence pessimism removal for paths with positive slack.
pt_shell> set_operating_conditions -analysis_type on_chip_variation WCCOM
pt_shell> set_timing_derate -min 0.8 -max 1.0
Example 2
This command sequence performs timing analysis for on-chip variation between two predefined operating conditions:WCCOM_scaled andWCCOM.It also performsclock reconvergence pessimism removal for paths with slack less than 0.4 ns.
pt_shell> set_operating_conditions -analysis_type on_chip_variation \
? -min WCCOM_scaled -max WCCOM
pt_shell> report_timing -remove_clock_reconvergence_pessimism 0.4
Example 3
This command sequence performs timing analysis for on-chip variation 5 percent above and 10 percent below the SDF backannotated
cell delays. For net delays, the on-chip variation is between 2 percent above and 4 percent belowtheSDFback-annotated values.
For timing delays, the on-chip variation for timing checks is 10 percent above the SDF values for setup and 20 percent belowthe SDF values for hold checks.
pt_shell> read_sdf -analysis_type on_chip_variation my_design.sdf
pt_shell> set_timing_derate -cell -min 0.90 -max 1.05
pt_shell> set_timing_derate -net -min 0.96 -max 1.02
pt_shell> set_timing_derate -cell_check -min 0.80 -max 1.10
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