Digital IC Design

BitCoin Donations are accepted

2011-06-22T20:16:00.004+08:00

My new blog addr: http://www.yanzhi.info/blog
Bitcoin Donations are accepted at 1Gwuhfzsm2qDEUUWQvx8WjhPBwehAoRhQx.

dropbox recommendation

2011-03-06T12:54:00.001+08:00

Sync your files online and across computers with @Dropbox. 2GB account is free! http://db.tt/bSicTC4
Backup your wordpress blog to Dropbox using the BackWPup plugin

2011 is comming

2010-12-24T20:12:00.001+08:00

Merry Christmas and Happy New Year!

Life will be Better and Better!

域名更改

2010-01-04T08:39:00.001+08:00

yanzhi.org -> yanzhi.info

blog addr: http://www.yanzhi.info/blog/

Sorry for any inconvenience!

Happy New Year

2009-12-31T16:17:00.001+08:00

Happy New Year!

多媒体SOC严重同质化

2009-12-21T16:24:00.001+08:00

cpu+video+graphic+image+audio+interface构成了一个高性能的soc，类似这样的芯片出了一颗又一颗，大部分核心ip都是license，这些产品的核心竞争力在哪呢？未来竞争力又体现在何处？做digital设计的人员出路又在何方？

目前可以说嵌入式软件是产品差异化中最重要的一环，但随着处理能力的进一步增强，嵌入式软件会不会有第二个微软出现？Android？到那时候，这些做多媒体soc的公司的竞争力又还剩什么？

restore source code encrypted by 'protectip'

2009-10-13T15:50:00.000+08:00

protectip from synplicity(in the synplify install directory) can encrypts VHDL and Verilog source files, it's a simple perl script which call the openssl for encryption.

The synplify tools can decrypt the source files before compiler, but the engineers can only read the encrypted text. so the ip be protected.

However, you can restore the source code if you got the password for ip encryption. I write the perl script for it.

Usage: decryptip

-in | input <Input File>

-out | output <Output File Name>

-c | cipher <Cipher - one of "des-cbc" "3des-cbc" "aes128-cbc">

-k | key <Symmetric Encryption Key in Text Format>

Example: ./decryptip -in protected_ip.v -out orig_ip.v -c des-cbc -k PASSWORD

click for download

IC设计书籍推荐

2009-09-20T00:03:00.001+08:00

做这个几年了，不知道算不算入门了。把一些曾经看过的书籍中觉得不错的推荐给大家。

其中有几本模拟和版图类的书籍是别人给推荐的。

根据当当网的资料做了个网页，以后会持续更新，http://www.yanzhi.org/blog/book.htm

linux防止误删除的简单办法[Tips]

2009-05-10T22:47:00.001+08:00

建立硬链接，ln 源文件【链接名】

硬链接的作用就是允许一个文件拥有多个有效路径名，直到删除最后一个链接文件才会真正被删除

Dirac-> vc-2 ?

2009-04-30T22:39:00.000+08:00

About Dirac

Dirac is an advanced royalty-free video compression format designed for a wide range of uses, from delivering low-resolution web content to broadcasting HD and beyond, to near-lossless studio editing.

The Dirac Project

Originally created by the BBC Research department, the Dirac project has expanded to include companies providing hardware equipment and software for handling Dirac video, as well as an active open-source development group.

Origin of the Name "Dirac"

The name "Dirac" is a reference to Paul A. M. Dirac, British physicist and winner of the 1933 Nobel Prize in Physics. The prize was shared with Erwin Schrödinger, for whom the Schroedinger implementation of Dirac was named.

硅谷模式未必适合本土创业公司【转自老杳吧】

2009-03-24T21:25:00.001+08:00

本人目前就职于一家本土集成电路创业公司，对这篇文章高度认同。

所谓硅谷集成电路创业模式一般包含三个阶段，一、获得VC对创意及团队认可，一般集成电路设计创业团队可以获得100-500万美元的启动资金创业；二、产品开发完成后创业公司会二次融资，额度一般在500-2000万美元用于产品推广；三、技术或产品获得市场认可后创业公司一般会选择直接IPO或被知名跨国公司收购，成功的硅谷创业公司一般都会经历上述三个阶段。

与硅谷模式不同，集成电路在中国发展几十年，上市的只有中星微、展讯和珠海炬力，能够被跨国公司收购的案例很少，十年前新涛科技被IDT以8500万美元收购以及上海掌微被Sirf 1.25亿美元收购之外鲜有成功，其实这两家也不能算是本土创业公司，总部都在硅谷，运营主体都设在美国，中国只设有部分研发，甚至所销售的产品也是以海外为主。

硅谷创业以核心技术为目标，能被跨国公司收购很正常，国内集成电路设计公司瞄准的是市场需求，至于技术是否领先则往往不是创业者最关注的，因此本土公司创业在技术层面很难引起跨国公司的关注，一旦开拓市场不利，被收购的价值为零，在中国集成电路设计界很少出现并购也是因为这个原因，因为中国集成电路设计公司有五百家之多，很多人预计未来会出现并购潮，老杳却认为很难，倒闭潮倒是非常有可能，真正拥有尖端核心技术的中国IC设计公司很少。

没有尖端核心技术并不能阻止本土IC设计公司的兴起，毕竟作为全球最大的电子产品制造基地，中国电子市场对不同种类、不同水准的集成电路需求非常旺盛，只有能够开发出适应市场需求的产品，即使没有最高端的技术本土IC设计公司一样可以做的非常不错，也是基于这一点，许多风险投资商认为中国是集成电路投资最后一片沃土。

与硅谷创业尽快开发出尖端技术不同，本土集成电路创业公司最大目标应当是尽快赚钱，无论产品高端低端，无论是否代表高科技，只有尽快实现营业收入，才能与客户建立紧密的关系，更好的把握市场脉搏，进而通过就客户推广新产品，目前阶段很多中国本土集成电路设计公司都是依赖中国成熟的电子制造产业生存，虽然产品品质与跨国公司相比略有差距，更好的性能价格比是竞争的根本，本土集成电路设计业的发展，反过来也促进了中国制造业的进步，制造出更加便宜、功能更加丰富的电子产品，应当说目前中国本土集成电路设计业已经与电子制造业形成了良好的互动和彼此依存的共生关系，山寨手机之所以流行，MTK固然居功至伟，中国本土集成电路设计业在成本上做的贡献同样不可小视，目前本土IC已经在FM、摄像头、蓝牙、电源管理、音频放大期，功率放大器、模拟电视甚至电池等部件上已经替代了或正在替代跨国公司成为主流供货商。其它诸如玩具用音频芯片等更在全球占据统治地位。

应当说本土IC更依赖市场而不是技术，这是本土IC创业公司与硅谷创业的最大区别，基于此本土创业者要更加重视市场和盈利，也正因为如此，本土集成电路设计公司被收购的价格会很低，这一点与电脑、电视领域的竞争格局并没有太大的区别。

虽然创业阶段本土与硅谷有较大的区别，如果希望成为一家伟大的公司，二者却殊途同归，说到底就像联想的"贸工技"和华为的"技工贸"的区别，拥有了市场的联想可以进一步拓展核心技术，这是本土IC发展的捷径，拥有了核心技术的华为进一步拓展市场，这是硅谷创业的归宿，当然如果创业公司无法最终生存，那又是另外一件事。(作者：老杳）

原帖地址：http://laoyaoba.com/wordpress/?p=2361

2009 Coming

2008-12-25T20:58:00.001+08:00

Merry Christmas & Happy New Year!

diff in linux

2008-12-24T20:49:00.002+08:00

diff在linux下用来比较两个文件或者文件夹的内容，具体使用可以参考http://linux.about.com/library/cmd/blcmdl1_diff.htm，其中-b可以比较不同类型的文件，如dos，unix，但经实践证明，如果两个文件类型不一样，且文件比较大，如大于1MB时，比较时间会很长，why?
如果我们把Windows下产生的文件在linux下执行一次dos2unix，转换成unix类型，然后再用diff比较，时间将大大减少。仅试过文本文件。

Virtex5 DSP48E Synplify8.6.2 bug?

2008-11-09T00:00:00.001+08:00

最近工作中遇到的一个问题，不知道是否是工具的bug，在此备案。
问题描述：设计中所用到的一个乘法器，在fpga验证时不能工作，用逻辑分析仪查看得知乘法器输入正确，但输出有问题。通过多次修改并用综合后的网表仿真得知是synplify在综合时调用DSP48E时处理出错，具体分析如下：
环境：Xilinx的Virtex5 LX系列FPGA，Synplify8.6.2综合，ISE9.2实现，Modelsim后仿
设计背景：乘法器的输入，一端为寄存器直接输出，另一端是比较复杂的组合逻辑，输出结果再做加法等运算，然后送入寄存器。
DSP48E简介：
Virtex-5 DSP48E Slice 包含 Virtex-4 DSP48 的所有功能以及多种新功能。这些新功能包括
一个更宽的 25 x 18 乘法器和一个扩展后用作逻辑单元的加/ 减功能。
看框图：

其中输入可以有两级寄存器，所以在做优化的时候会把外面的寄存器放到里面，而这两级寄存器分别有两个EN端，当只用其中一个时，会使用REG2，可以从仿真的model中间可以看到详细的描述，但Synpilfy在处理这种情况时，使用的是REG1 ，此时CE2常为1，所以导致输入数据不能在正确的时刻被latch，进而导致输出错误。
在搜索时发现Xilinx自己的工具，如coregen之类的在处理DSP48E时也出现过不少bug，synplify也是从8.6版本才开始支持virtex5的，所以我觉得很有可能是工具在这有bug，目前synplify的版本已达9.6以上，估计新版本不会再有此问题。
总结：
1、尽量不要用工具最新的功能，关注工具新版的release notes
2、FPGA做逻辑验证的时候最好不要使用FPGA的特殊单元，也不要让工具做太多的优化，除非timing确实有问题
3、出了问题应该先分析问题，不要一上来就尝试各种修改的办法。（这点我开始认为自己的coding style有问题，让工具犯傻了，所以修改了好几次，均已失败告终）

IPcore Release Package

2008-09-30T08:42:00.001+08:00

IPcore Release Package Should include:

Synthesizable Verilog RTL
Bit-accurate C model
Verilog testbench
Detailed product documentation
Design specifications
Integration guidelines
Complete verification suite
VHS tape with example noisy signals
Extensive tests including corner-case scenarios
Golden test result vectors
FPGA test board (with testbench and supporting files)
Support and training
to be added...

清除所有.svn目录

2008-09-29T08:34:00.001+08:00

一、在linux下

删除这些目录是很简单的，命令如下
find . -type d -name ".svn"|xargs rm -rf

或者

find . -type d -iname ".svn" -exec rm -rf {} \;

全部搞定。

二、在windows下

1、在项目平级的目录，执行dos命令：
xcopy project_dir project_dir_1 /s /i

2、或者在项目根目录执行以下dos命令
for /r . %%a in (.) do @if exist "%%a\.svn" rd /s /q "%%a\.svn"

3、直接用windows的搜索功能，打开搜索隐藏文件的选项，然后搜索.svn，再一起删除即可

Power Savings Techniques

2008-09-27T20:07:00.001+08:00

From snug San Jose -- Power Analysis Methodology
From Spreadsheet to Sign-off by George Cuan, Cisco Systems, Inc.

async fifo design

2008-08-31T22:53:00.001+08:00

Key points:
1. fifo body: dual ports sram or registers array
2. read and write address for sram
3. empty and full flag for the fifo body, it's the most important, and there are two methods presented in the reference paper.
4. almost empty or almost full flag, if needed
5. fifo content depth or fifo space depth, if needed
6. some special case for the special application, eg. the predicable r/w clock frequence ratio.

Reference paper:
http://www.sunburst-design.com/papers/

H.264 Baseline Decoder from opencores

2008-06-05T11:03:00.001+08:00

Nova is a low-power realtime H.264/AVC baseline decoder of QCIF resolution, targeting mobile applications. It is a dedicated, full hardwired and self-contained ASIC design without utilizing any GPP/DSP cores. It has been successfully verified on Xilinx Virtex-4 FPGA and 0.18um ASIC chip. The measured power consumption is 293uW@1V for 30fps QCIF decoding.

Introduction page:http://www.opencores.org/projects.cgi/web/nova/overview

source code download[http]:http://www.ipcore.cn

Berkeley University EECS Course WEB Sites

2008-05-28T22:20:00.001+08:00

http://inst.eecs.berkeley.edu/classes-eecs.html

There are many EE classes online, so good for the EE students and RDs.

EECS1 Introduction to EECS
EECSBA1 Strategic Computing and Communications Technology
EECS20N Structure and Interpretation of Systems and Signals
EE24 Freshman Seminar
EE40 Introduction to Microelectronic Circuits
EE42 Introduction to Digital Electronics
EE43 Introductory Electronics Laboratory
EE98 EE 98 Seminar Home Pages
EE100 Electronic Techniques for Engineering
EE104 Linear and Nonlinear Circuits
EE105 Microelectronic Devices and Circuits
EE117 Electromagnetic Fields and Waves
EE117B Electromagnetic Fields and Waves II
EE118 Introduction to Optical Communication Systems
EE119 Introduction to Optical Engineering
EECS120 Signals and Systems
EE121 Introduction to Digital Communication Systems
EE122 Introduction to Communication Networks
EE123 Digital Signal Processing
EE125 Introduction to Robotics
EE126 Probability and Random Processes
EE128 Feedback Control
EE129 Neural and Nonlinear Information Processing
EE130 Integrated-Circuit Devices
EE131 Semiconductor Electronics
EE136 Introduction to Quantum and Optical Electronics
EE140 Linear Integrated Circuits
EE141 Introduction to Digital Integrated Circuits
EE142 Integrated Circuits for Communications
EE143 Microfabrication Technology
EE145L Introductory Electronic Transducers Laboratory
EE145M Intro Microcomputer Interfacing Lab
EE145A (renamed to EE145L)
EE145B Image Processing and Reconstruction Tomography
EE146 unknown
EECS150 Components and Design Techniques for Digital System...
EECS152 Computer Architecture and Engineering
EE192 Mechatronics
EE194 EE 194 Seminar Home Pages
EEH196A Senior Honors Thesis Research
EE198 EE 198 Seminar Home Pages
EE199 Independent Study
EE201 Strategic Computing and Communications Technology
EE210 Applied Electromagnetic Theory
EE210B Applied Electromagnetic Theory
EE213 Soft X-Rays and Extreme Ultraviolet Radiation
EE217 Microwave Circuits
EE219 unknown
EE219A Computer-Aided Verification of Electronic Circuits
EE219B Logic Synthesis for Hardware Systems
EE219C Computer-Aided Verification
EE220 Neural & Nonlinear Information Processing
EE221A Linear System Theory
EE222 Nonlinear Systems--Analysis, Stability and Control
EE223 Stochastic Systems: Estimation and Control
EE224A Digital Communications
EE224B Fundamentals of Wireless Communications
EE225D Audio Signal Processing
EE225A Digital Signal Processing
EE225B Digital Image Processing
EE225C VLSI Signal Processing
EE226 unknown
EE226A Random Processes in Systems
EE227A Introduction to Convex Optimization
EE228A Communication Networks
EE229 Information Theory and Coding
EE229B Error Control Coding
EE230 Solid State Electronics
EE231 Solid State Devices
EE232 Lightwave Devices
EE233 Lightwave Systems
EE235 Nanoscale Fabrication
EE236A Quantum and Optical Electronics
EE238 Superconductive Devices and Circuits
EE240 Analog Integrated Circuit Design and Analysis
EE241 Advanced Digital Integrated Circuits
EE242 Advanced Integrated Circuits for Communications
EE243 Advanced IC Processing and Layout
EE244 Computer-Aided Design of Integrated Circuits
EECS245 Introduction to MEMS Design
EE246 Microelectromechanical Systems (MEMS)
EE247 Analysis and Design of VLSI Analog-Digital Interfac...
EE249 Embedded System Design
EE290D Advanced Topics in Semiconductor Technology
EE290E Advanced Topics in Electromagnetics and Plasmas
EE290F Advanced Topics
EE290G (renamed to EE245)
EE290H Semiconductor Manufacturing
EE290I Advanced Topics in Wireless Communication
EE290J Advanced Topics in Electrical Engineering
EE290N Advanced Topics in System Theory
EE290O Advanced Topics in Control
EE290Q Advanced Topics in Communication Networks
EE290S Advanced Topics in Communications and Information T...
EE290T Advanced Topics in Signal Processing
EE290X Advanced Topics in Management and Social Issues in ...
EE290Y Organic Materials in Electronics
EE290A Advanced Topics in Computer-Aided Design
EE290B Advanced Topics in Solid State Devices
EE290C Advanced Topics in Circuit Design
EE291 Control and Optimization of Distributed Parameters ...
EE291E Hybrid Systems and Intelligent Control
EE297 Field Studies in Electrical Engineering
EE298 EE 298 Seminar Home Pages
EE299 Individual Research
EE301 Teaching Techniques for Electrical Engineering

Support earthquake relief in China

2008-05-22T20:28:00.002+08:00

From:http://en.wikipedia.org/wiki/2008_Sichuan_earthquake

The 2008 Sichuan earthquake (Chinese: 四川大地震), which measured at 8.0 Ms according to the China Seismological Bureau, and 7.9 Mw according to USGS, occurred at 14:28:01.42 CST (06:28:01.42 UTC) on 12 May 2008 in Sichuan province of China. It was also known as the Wenchuan earthquake (Chinese: 汶川大地震), after the earthquake's epicenter in Wenchuan County in Sichuan province. The epicenter was 80 kilometres (50 mi) west-northwest of Chengdu, the capital of Sichuan, with a depth of 19 kilometres (12 mi).[2] The earthquake was felt as far away as Beijing (1,500 km away) and Shanghai (1,700 km away), where office buildings swayed with the tremor.[5] The earthquake was also felt in nearby countries.
Official figures (as of May 22, 10:00 CST) state that 51,151 are confirmed dead, including 50,651 in Sichuan province, and 288,431 injured.[4] Tens of thousands are missing, approximately 14,000 of them buried, and eight provinces were affected.[6] The earthquake left about 4.8 million people homeless.[7] It was the deadliest and strongest earthquake to hit China since the 1976 Tangshan earthquake, which killed over 240,000 people.

Support earthquake relief in China

http://www.google.com/chinaearthquake/

registered output

2008-03-10T21:04:00.001+08:00

最近项目碰到的一个问题，设计时没用寄存器输出，导致接口部分由于时序问题出错。就此问题谈点自己的看法。

一般来说，我们只是在芯片的接口处考虑寄存器输出，因为内部逻辑都能在EDA工具的控制较好地保证timing，但接口处由于对方的逻辑未知，无法保证timing，在某些case可能会出现timing出错的问题。

当项目较大时，综合不能完全top-down，此时在IP的顶层最好也用寄存器输出，以简化IP间接口timing的check。

IP内部的话，不一定非得寄存器输出不可。很多初学者为了简单起见，只要是输出都加上寄存器，这样会浪费面积，而且有时电路的效率也会降低（delay1T）。

总的来说，是否需要寄存器输出虽是个小问题，但对于高效稳定的设计，任何小问题都不得放过。

How to do Statistical Timing Analysis for a Path that Includes Clock-shaping Circuit

2008-01-17T11:38:00.001+08:00

Question:
I have a pulse-shaping circuit similar to the one shown in the following figure.
In the following circuit, only the falling edge from and1/A and rising edge from
and1/B should be used (see waveforms).

How should this be modelled in PrimeTime?
Answer:
This can be done using the set_case_analysis command and assigning values "falling"
to and1/A and "rising" for and1/B. A sample verilog netlist, a set of constraint
and the timing reports are shown below to demonstrate the behaviour.
//Verilog netlist
module clock_shape (in,out);
input in;
output out;
buf1a1 b1 (.A(in), .Y(u1_out));
buf1a1 b2 (.A(u1_out), .Y(u2_out));
buf1a1 b3 (.A(u2_out), .Y(u3_out));
and2a1 and1 (.A(in), .B(u3_out),.Y(out));
endmodule
#Constraints
create_clock -p 1 -name clk
set_input_delay -clock clk 0 [all_inputs]
set_output_delay -clock clk 0 [all_outputs]
set_case_analysis falling [get_pin and1/A]
set_case_analysis rising [get_pin and1/B]
report_timing -input_pins -fall_to out
report_timing -input_pins -rise_to out
report_timing -input_pins -through and1/A -fall_to out
#Reports
pt_shell> report_timing -input_pins -fall_to out
****************************************
Report : timing
-path_type full
-delay_type max
-input_pins
-max_paths 1
Design : clock_shape
Version: Z-2007.06-SP2
Date : Thu Oct 4 16:03:46 2007
****************************************
Startpoint: in (input port clocked by clk)
Endpoint: out (output port clocked by clk)
Path Group: clk
Path Type: max
Point Incr Path
---------------------------------------------------------------
clock clk (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
input external delay 0.00 0.00 f
in (in) 0.00 0.00 f
and1/A (and2a1) 0.00 0.00 f
and1/Y (and2a1) 0.12 0.12 f
out (out) 0.00 0.12 f
data arrival time 0.12
clock clk (rise edge) 1.00 1.00
clock network delay (ideal) 0.00 1.00
output external delay 0.00 1.00
data required time 1.00
---------------------------------------------------------------
data required time 1.00
data arrival time -0.12
---------------------------------------------------------------
slack (MET) 0.88
1
pt_shell> report_timing -input_pins -rise_to out
****************************************
Report : timing
-path_type full
-delay_type max
-input_pins
-max_paths 1
Design : clock_shape
Version: Z-2007.06-SP2
Date : Thu Oct 4 16:04:25 2007
****************************************
Startpoint: in (input port clocked by clk)
Endpoint: out (output port clocked by clk)
Path Group: clk
Path Type: max
Point Incr Path
---------------------------------------------------------------
clock clk (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
input external delay 0.00 0.00 r
in (in) 0.00 0.00 r
b1/A (buf1a1) 0.00 0.00 r
b1/Y (buf1a1) 0.14 0.14 r
b2/A (buf1a1) 0.00 0.14 r
b2/Y (buf1a1) 0.18 0.32 r
b3/A (buf1a1) 0.00 0.32 r
b3/Y (buf1a1) 0.18 0.50 r
and1/B (and2a1) 0.00 0.50 r
and1/Y (and2a1) 0.18 0.68 r
out (out) 0.00 0.68 r
data arrival time 0.68
clock clk (rise edge) 1.00 1.00
clock network delay (ideal) 0.00 1.00
output external delay 0.00 1.00
data required time 1.00
---------------------------------------------------------------
data required time 1.00
data arrival time -0.68
---------------------------------------------------------------
slack (MET) 0.32
1
pt_shell> report_timing -input_pins -through and1/A -rise_to out
****************************************
Report : timing
-path_type full
-delay_type max
-input_pins
-max_paths 1
Design : clock_shape
Version: Z-2007.06-SP2
Date : Thu Oct 4 16:04:57 2007
****************************************
No constrained paths.
1

some video ebook links

2007-12-31T21:37:00.001+08:00

1.Title: Video Codec Design: Developing Image and Video Compression Systems
Author: Iain Richardson
ISBN: 0471485535
http://rapidshare.com/files/21088581/110_0471485535_Video.rar
Password: free4vn.org

2.Title: Video Demystified, Fourth Edition (Demystifying Technology)
Author: Keith Jack
ISBN: 0750678224
http://rapidshare.com/files/21081509/
303_0750678224_JACK__K.__2001_._Video_Demystified_-_A_Handbook_for_the_Digital_Engineer__3rd_ed._.rar
Password: free4vn.org

3.Title: Digital Video Solutions (Solutions)
Author: Winston Steward
ISBN: 192968553X
Detail: Amazon
http://rapidshare.com/files/21087696/1411_192968553X_Digi.rar
Password: free4vn.org

4.Title: Video Coding with Superimposed Motion-Compensated Signals : Applications to H.264 and Beyond(The International Series in Engineering and Computer Science)
Author: Markus Flierl
ISBN: 1402077599
http://rapidshare.com/files/21087711/1409_1402077599_321.rar
Password: free4vn.org

5.Title: Digital Video Broadcasting: Technology, Standards, and Regulations
Author: Ronald de Bruin
ISBN: 0890067430
http://rapidshare.com/files/21087690/1406_0890067430_123.rar
Password: free4vn.org

6.Title: Real-Time Video Compression : Techniques and Algorithms (The International Series in Engineering and Computer Science)
Author: Raymond Westwater
ISBN: 0792397878
http://rapidshare.com/files/21087691/1408_0792397878_efg.rar
Password: free4vn.org

7.Title: Video Data (Innovative Technology Series)
Author: Salima Hassas
ISBN: 1903996228
http://rapidshare.com/files/21087692/1410_1903996228_edc.rar
Password: free4vn.org

Merry Christmas and Happy New Year

2007-12-24T08:44:00.001+08:00

Merry Christmas and Happy New Year!

IC封装

2007-12-13T13:35:00.001+08:00

芯片设计规划时要考虑到一个重要因素---封装。

[转载]来源：PCB 技术作者：sjb21ic
1、BGA(ball grid array)
球形触点陈列，表面贴装型封装之一。在印刷基板的背面按陈列方式制作出球形凸点用以代替引脚，在印刷基板的正面装配LSI 芯片，然后用模压树脂或灌封方法进行密封。也称为凸点陈列载体(PAC) 。引脚可超过200，是多引脚LSI 用的一种封装。
封装本体也可做得比QFP(四侧引脚扁平封装)小。例如，引脚中心距为 1.5mm 的360 引脚 BGA 仅为 31mm 见方；而引脚中心距为0.5mm 的304 引脚QFP 为40mm 见方。而且BGA 不用担心QFP 那样的引脚变形问题。
该封装是美国 Motorola 公司开发的，首先在便携式电话等设备中被采用，今后在美国有可能在个人计算机中普及。最初，BGA 的引脚 (凸点)中心距为1.5mm，引脚数为225 。现在也有一些LSI 厂家正在开发500 引脚的BGA。
BGA 的问题是回流焊后的外观检查。现在尚不清楚是否有效的外观检查方法。有的认为，由于焊接的中心距较大，连接可以看作是稳定的，只能通过功能检查来处理。
美国Motorola 公司把用模压树脂密封的封装称为OMPAC，而把灌封方法密封的封装称为 GPAC( 见OMPAC 和GPAC)。

2、 BQFP(quad flat package with bumper)
带缓冲垫的四侧引脚扁平封装。QFP 封装之一，在封装本体的四个角设置突起 (缓冲垫)以防止在运送过程中引脚发生弯曲变形。美国半导体厂家主要在微处理器和ASIC 等电路中采用此封装。引脚中心距0.635mm，引脚数从84 到196 左右(见QFP)。

3 、碰焊PGA(butt joint pin grid array)
表面贴装型PGA 的别称( 见表面贴装型PGA)。

4、C－ (ceramic)
表示陶瓷封装的记号。例如，CDIP 表示的是陶瓷DIP 。是在实际中经常使用的记号。

5、Cerdip
用玻璃密封的陶瓷双列直插式封装，用于ECL RAM ，DSP(数字信号处理器)等电路。带有玻璃窗口的Cerdip 用于紫外线擦除型EPROM 以及内部带有EPROM 的微机电路等。引脚中心距 2.54mm，引脚数从8 到42。在日本，此封装表示为DIP －G(G 即玻璃密封的意思)。

6 、Cerquad
表面贴装型封装之一，即用下密封的陶瓷QFP，用于封装 DSP 等的逻辑LSI 电路。带有窗口的Cerquad 用于封装 EPROM 电路。散热性比塑料QFP 好，在自然空冷条件下可容许1.5～ 2W 的功率。但封装成本比塑料QFP 高3～5 倍。引脚中心距有1.27mm、0.8mm、0.65mm 、0.5mm、0.4mm 等多种规格。引脚数从32 到368。

7、CLCC(ceramic leaded chip carrier)
带引脚的陶瓷芯片载体，表面贴装型封装之一，引脚从封装的四个侧面引出，呈丁字形。带有窗口的用于封装紫外线擦除型EPROM 以及带有EPROM 的微机电路等。此封装也称为 QFJ、QFJ－G(见QFJ) 。

8、COB(chip on board)
板上芯片封装，是裸芯片贴装技术之一，半导体芯片交接贴装在印刷线路板上，芯片与基板的电气连接用引线缝合方法实现，芯片与基板的电气连接用引线缝合方法实现，并用树脂覆盖以确保可靠性。虽然COB 是最简单的裸芯片贴装技术，但它的封装密度远不如TAB 和倒片焊技术。

9、DFP(dual flat package)
双侧引脚扁平封装。是SOP 的别称(见SOP)。以前曾有此称法，现在已基本上不用。

10 、DIC(dual in-line ceramic package)
陶瓷DIP(含玻璃密封) 的别称(见DIP).

11、DIL(dual in-line)
DIP 的别称(见DIP)。欧洲半导体厂家多用此名称。

12 、DIP(dual in-line package)
双列直插式封装。插装型封装之一，引脚从封装两侧引出，封装材料有塑料和陶瓷两种。 DIP 是最普及的插装型封装，应用范围包括标准逻辑 IC，存贮器LSI，微机电路等。引脚中心距2.54mm，引脚数从 6 到64。封装宽度通常为15.2mm。有的把宽度为 7.52mm 和10.16mm 的封装分别称为 skinny DIP 和slim DIP(窄体型DIP)。但多数情况下并不加区分，只简单地统称为DIP。另外，用低熔点玻璃密封的陶瓷DIP 也称为cerdip( 见cerdip)。

13、DSO(dual small out-lint)
双侧引脚小外形封装。SOP 的别称(见SOP)。部分半导体厂家采用此名称。

14、DICP(dual tape carrier package)
双侧引脚带载封装。TCP( 带载封装)之一。引脚制作在绝缘带上并从封装两侧引出。由于利用的是TAB(自动带载焊接 )技术，封装外形非常薄。常用于液晶显示驱动LSI，但多数为定制品。另外，0.5mm 厚的存储器LSI 簿形封装正处于开发阶段。在日本，按照EIAJ(日本电子机械工业) 会标准规定，将DICP 命名为DTP。

15 、DIP(dual tape carrier package)
同上。日本电子机械工业会标准对DTCP 的命名( 见DTCP)。

16、FP(flat package)
扁平封装。表面贴装型封装之一。QFP 或SOP(见 QFP 和SOP)的别称。部分半导体厂家采用此名称。

17、 flip-chip
倒焊芯片。裸芯片封装技术之一，在LSI 芯片的电极区制作好金属凸点，然后把金属凸点与印刷基板上的电极区进行压焊连接。封装的占有面积基本上与芯片尺寸相同。是所有封装技
术中体积最小、最薄的一种。但如果基板的热膨胀系数与LSI 芯片不同，就会在接合处产生反应，从而影响连接的可靠性。因此必须用树脂来加固LSI 芯片，并使用热膨胀系数基本相同的基板材料。

18、FQFP(fine pitch quad flat package)
小引脚中心距 QFP。通常指引脚中心距小于0.65mm 的QFP(见 QFP)。部分导导体厂家采用此名称。

19、CPAC(globe top pad array carrier)
美国Motorola 公司对BGA 的别称( 见BGA)。

20、CQFP(quad fiat package with guard ring)
带保护环的四侧引脚扁平封装。塑料QFP 之一，引脚用树脂保护环掩蔽，以防止弯曲变形。在把LSI 组装在印刷基板上之前，从保护环处切断引脚并使其成为海鸥翼状(L 形状)。这种封装在美国Motorola 公司已批量生产。引脚中心距0.5mm，引脚数最多为208 左右。

21 、H-(with heat sink)
表示带散热器的标记。例如，HSOP 表示带散热器的SOP 。

22、pin grid array(surface mount type)
表面贴装型PGA 。通常PGA 为插装型封装，引脚长约3.4mm。表面贴装型PGA 在封装的底面有陈列状的引脚，其长度从1.5mm 到2.0mm。贴装采用与印刷基板碰焊的方法，因而也称为碰焊 PGA。因为引脚中心距只有1.27mm，比插装型PGA 小一半，所以封装本体可制作得不怎么大，而引脚数比插装型多 (250～528)，是大规模逻辑LSI 用的封装。封装的基材有多层陶瓷基板和玻璃环氧树脂印刷基数。以多层陶瓷基材制作封装已经实用化。

23、JLCC(J-leaded chip carrier)
J 形引脚芯片载体。指带窗口CLCC 和带窗口的陶瓷QFJ 的别称(见CLCC 和QFJ)。部分半导体厂家采用的名称。

24、 LCC(Leadless chip carrier)
无引脚芯片载体。指陶瓷基板的四个侧面只有电极接触而无引脚的表面贴装型封装。是高速和高频IC 用封装，也称为陶瓷QFN 或QFN－C(见QFN) 。

25、LGA(land grid array)
触点陈列封装。即在底面制作有阵列状态坦电极触点的封装。装配时插入插座即可。现已实用的有227 触点(1.27mm 中心距)和 447 触点(2.54mm 中心距)的陶瓷 LGA，应用于高速逻辑 LSI 电路。LGA 与QFP 相比，能够以比较小的封装容纳更多的输入输出引脚。另外，由于引线的阻抗小，对于高速LSI 是很适用的。但由于插座制作复杂，成本高，现在基本上不怎么使用。预计今后对其需求会有所增加。

26 、LOC(lead on chip)
芯片上引线封装。LSI 封装技术之一，引线框架的前端处于芯片上方的一种结构，芯片的中心附近制作有凸焊点，用引线缝合进行电气连接。与原来把引线框架布置在芯片侧面附近的结构相比，在相同大小的封装中容纳的芯片达1mm 左右宽度。

27 、LQFP(low profile quad flat package)
薄型QFP。指封装本体厚度为1.4mm 的QFP，是日本电子机械工业会根据制定的新QFP外形规格所用的名称。

28、L－QUAD
陶瓷 QFP 之一。封装基板用氮化铝，基导热率比氧化铝高7～8 倍，具有较好的散热性。封装的框架用氧化铝，芯片用灌封法密封，从而抑制了成本。是为逻辑 LSI 开发的一种封装，在自然空冷条件下可容许W3的功率。现已开发出了 208 引脚(0.5mm 中心距)和160 引脚(0.65mm中心距)的LSI 逻辑用封装，并于1993 年10 月开始投入批量生产。

29 、MCM(multi-chip module)
多芯片组件。将多块半导体裸芯片组装在一块布线基板上的一种封装。根据基板材料可分为MCM－ L，MCM－C 和MCM －D 三大类。
MCM－L 是使用通常的玻璃环氧树脂多层印刷基板的组件。布线密度不怎么高，成本较低。
MCM－C 是用厚膜技术形成多层布线，以陶瓷(氧化铝或玻璃陶瓷 )作为基板的组件，与使
用多层陶瓷基板的厚膜混合IC 类似。两者无明显差别。布线密度高于MCM－L。
MCM －D 是用薄膜技术形成多层布线，以陶瓷(氧化铝或氮化铝)或 Si、Al 作为基板的组件。
布线密谋在三种组件中是最高的，但成本也高。

30、MFP(mini flat package)
小形扁平封装。塑料SOP 或SSOP 的别称(见SOP 和 SSOP)。部分半导体厂家采用的名称。

31、MQFP(metric quad flat package)
按照JEDEC(美国联合电子设备委员会)标准对QFP 进行的一种分类。指引脚中心距为 0.65mm、本体厚度为3.8mm～2.0mm 的标准QFP(见QFP)。

32、 MQUAD(metal quad)
美国Olin 公司开发的一种QFP 封装。基板与封盖均采用铝材，用粘合剂密封。在自然空冷条件下可容许2.5W～2.8W 的功率。日本新光电气工业公司于 1993 年获得特许开始生产。

33、MSP(mini square package)
QFI 的别称(见QFI)，在开发初期多称为MSP 。QFI 是日本电子机械工业会规定的名称。

34、OPMAC(over molded pad array carrier)
模压树脂密封凸点陈列载体。美国Motorola 公司对模压树脂密封BGA 采用的名称 (见 BGA)。

35、P －(plastic)
表示塑料封装的记号。如PDIP 表示塑料DIP 。

36、PAC(pad array carrier)
凸点陈列载体，BGA 的别称(见BGA)。

37、 PCLP(printed circuit board leadless package)
印刷电路板无引线封装。日本富士通公司对塑料QFN(塑料 LCC)采用的名称(见QFN)。引脚中心距有0.55mm 和0.4mm 两种规格。目前正处于开发阶段。

38 、PFPF(plastic flat package)
塑料扁平封装。塑料QFP 的别称( 见QFP)。部分LSI 厂家采用的名称。

39 、PGA(pin grid array)
陈列引脚封装。插装型封装之一，其底面的垂直引脚呈陈列状排列。封装基材基本上都采用多层陶瓷基板。在未专门表示出材料名称的情况下，多数为陶瓷PGA ，用于高速大规模逻辑LSI 电路。成本较高。引脚中心距通常为2.54mm，引脚数从64 到447 左右。了为降低成本，封装基材可用玻璃环氧树脂印刷基板代替。也有64～ 256 引脚的塑料PGA。另外，还有一种引脚中心距为1.27mm 的短引脚表面贴装型PGA(碰焊PGA)。( 见表面贴装型PGA)。

40、piggy back
驮载封装。指配有插座的陶瓷封装，形关与DIP、QFP、QFN 相似。在开发带有微机的设备时用于评价程序确认操作。例如，将EPROM 插入插座进行调试。这种封装基本上都是定制品，市场上不怎么流通。

41 、PLCC(plastic leaded chip carrier)
带引线的塑料芯片载体。表面贴装型封装之一。引脚从封装的四个侧面引出，呈丁字形，是塑料制品。美国德克萨斯仪器公司首先在64k 位DRAM 和256kDRAM 中采用，现在已经普及用于逻辑LSI 、DLD(或程逻辑器件)等电路。引脚中心距1.27mm，引脚数从 18 到84。 J 形引脚不易变形，比 QFP 容易操作，但焊接后的外观检查较为困难。
PLCC 与LCC(也称 QFN)相似。以前，两者的区别仅在于前者用塑料，后者用陶瓷。但现在已经出现用陶瓷制作的J 形引脚封装和用塑料制作的无引脚封装( 标记为塑料LCC、PCLP、P－ LCC 等)，已经无法分辨。为此，日本电子机械工业会于1988 年决定，把从四侧引出 J 形引脚的封装称为QFJ，把在四侧带有电极凸点的封装称为QFN(见 QFJ 和QFN)。

42、P －LCC(plastic teadless chip carrier)(plastic leaded chip currier)
有时候是塑料QFJ 的别称，有时候是QFN(塑料LCC)的别称(见 QFJ 和QFN)。部分LSI 厂家用 PLCC 表示带引线封装，用P－LCC 表示无引线封装，以示区别。

43、QFH(quad flat high package)
四侧引脚厚体扁平封装。塑料QFP 的一种，为了防止封装本体断裂，QFP 本体制作得
较厚( 见QFP)。部分半导体厂家采用的名称。

44、QFI(quad flat I-leaded packgac)
四侧I 形引脚扁平封装。表面贴装型封装之一。引脚从封装四个侧面引出，向下呈I 字。也称为MSP(见MSP)。贴装与印刷基板进行碰焊连接。由于引脚无突出部分，贴装占有面积小于QFP 。日立制作所为视频模拟IC 开发并使用了这种封装。此外，日本的Motorola 公司的PLL IC 也采用了此种封装。引脚中心距1.27mm，引脚数从18 于68 。

45、QFJ(quad flat J-leaded package)
四侧J 形引脚扁平封装。表面贴装封装之一。引脚从封装四个侧面引出，向下呈J 字形。是日本电子机械工业会规定的名称。引脚中心距1.27mm。材料有塑料和陶瓷两种。塑料 QFJ 多数情况称为PLCC(见PLCC)，用于微机、门陈列、 DRAM、ASSP、OTP 等电路。引脚数从18 至84。陶瓷QFJ 也称为CLCC 、JLCC(见CLCC)。带窗口的封装用于紫外线擦除型EPROM 以及带有EPROM 的微机芯片电路。引脚数从32 至84。

46、QFN(quad flat non-leaded package)
四侧无引脚扁平封装。表面贴装型封装之一。现在多称为 LCC。QFN 是日本电子机械工业会规定的名称。封装四侧配置有电极触点，由于无引脚，贴装占有面积比QFP 小，高度比 QFP 低。但是，当印刷基板与封装之间产生应力时，在电极接触处就不能得到缓解。因此电极触点难于作到QFP 的引脚那样多，一般从14 到100 左右。材料有陶瓷和塑料两种。当有LCC 标记时基本上都是陶瓷QFN 。电极触点中心距1.27mm。塑料QFN 是以玻璃环氧树脂印刷基板基材的一种低成本封装。电极触点中心距除 1.27mm 外，还有0.65mm 和0.5mm 两种。这种封装也称为塑料LCC、PCLC、 P－LCC 等。

47、 QFP(quad flat package)
四侧引脚扁平封装。表面贴装型封装之一，引脚从四个侧面引出呈海鸥翼(L)型。基材有陶瓷、金属和塑料三种。从数量上看，塑料封装占绝大部分。当没有特别表示出材料时，多数情况为塑料 QFP。塑料QFP 是最普及的多引脚LSI 封装。不仅用于微处理器，门陈列等数字逻辑 LSI 电路，而且也用于VTR 信号处理、音响信号处理等模拟LSI 电路。引脚中心距有1.0mm、0.8mm、0.65mm、 0.5mm、0.4mm、0.3mm 等多种规格。0.65mm 中心距规格中最多引脚数为304。日本将引脚中心距小于0.65mm 的QFP 称为QFP(FP)。但现在日本电子机械工业会对 QFP的外形规格进行了重新评价。在引脚中心距上不加区别，而是根据封装本体厚度分为QFP(2.0mm～3.6mm 厚)、LQFP(1.4mm 厚) 和TQFP(1.0mm 厚)三种。另外，有的LSI 厂家把引脚中心距为0.5mm 的QFP 专门称为收缩型 QFP 或SQFP、VQFP。但有的厂家把引脚中心距为 0.65mm 及0.4mm 的 QFP 也称为SQFP，至使名称稍有一些混乱。 QFP 的缺点是，当引脚中心距小于 0.65mm 时，引脚容易弯曲。为了防止引脚变形，现已出现了几种改进的QFP 品种。如封装的四个角带有树指缓冲垫的BQFP( 见BQFP)；带树脂保护环覆盖引脚前端的GQFP(见GQFP) ；在封装本体里设置测试凸点、放在防止引脚变形的专用夹具里就可进行测试的TPQFP(见TPQFP)。在逻辑 LSI 方面，不少开发品和高可靠品都封装在多层陶瓷QFP 里。引脚中心距最小为 0.4mm、引脚数最多为 348 的产品也已问世。此外，也有用玻璃密封的陶瓷QFP(见Gerqad) 。

48、QFP(FP)(QFP fine pitch)
小中心距QFP 。日本电子机械工业会标准所规定的名称。指引脚中心距为0.55mm、0.4mm、 0.3mm 等小于0.65mm 的QFP(见 QFP)。

49、QIC(quad in-line ceramic package)
陶瓷QFP 的别称。部分半导体厂家采用的名称(见QFP、 Cerquad)。

50、QIP(quad in-line plastic package)
塑料QFP 的别称。部分半导体厂家采用的名称(见QFP)。

51、QTCP(quad tape carrier package)
四侧引脚带载封装。TCP 封装之一，在绝缘带上形成引脚并从封装四个侧面引出。是利用 TAB 技术的薄型封装(见 TAB、TCP)。

52、QTP(quad tape carrier package)
四侧引脚带载封装。日本电子机械工业会于1993 年4 月对 QTCP 所制定的外形规格所用的名称(见TCP) 。

53、QUIL(quad in-line)
QUIP 的别称( 见QUIP)。

54、QUIP(quad in-line package)
四列引脚直插式封装。引脚从封装两个侧面引出，每隔一根交错向下弯曲成四列。引脚中心距1.27mm，当插入印刷基板时，插入中心距就变成2.5mm。因此可用于标准印刷线路板。是比标准 DIP 更小的一种封装。日本电气公司在台式计算机和家电产品等的微机芯片中采用了些种封装。材料有陶瓷和塑料两种。引脚数64。

55 、SDIP (shrink dual in-line package)
收缩型DIP。插装型封装之一，形状与 DIP 相同，但引脚中心距(1.778mm)小于DIP(2.54mm)，因而得此称呼。引脚数从14 到90。也有称为SH －DIP 的。材料有陶瓷和塑料两种。

56、SH －DIP(shrink dual in-line package)
同SDIP。部分半导体厂家采用的名称。

57、SIL(single in-line)
SIP 的别称( 见SIP)。欧洲半导体厂家多采用SIL 这个名称。

58 、SIMM(single in-line memory module)
单列存贮器组件。只在印刷基板的一个侧面附近配有电极的存贮器组件。通常指插入插座的组件。标准SIMM 有中心距为 2.54mm 的30 电极和中心距为1.27mm 的72 电极两种规格。在印刷基板的单面或双面装有用SOJ 封装的1 兆位及4 兆位DRAM 的 SIMM 已经在个人计算机、工作站等设备中获得广泛应用。至少有30～40 ％的DRAM 都装配在SIMM 里。

59 、SIP(single in-line package)
单列直插式封装。引脚从封装一个侧面引出，排列成一条直线。当装配到印刷基板上时封装呈侧立状。引脚中心距通常为2.54mm ，引脚数从2 至23，多数为定制产品。封装的形状各异。也有的把形状与ZIP 相同的封装称为SIP。

60 、SK－DIP(skinny dual in-line package)
DIP 的一种。指宽度为7.62mm 、引脚中心距为2.54mm 的窄体DIP。通常统称为DIP( 见DIP)。

61、SL－ DIP(slim dual in-line package)
DIP 的一种。指宽度为10.16mm，引脚中心距为2.54mm 的窄体DIP。通常统称为DIP。

62 、SMD(surface mount devices)
表面贴装器件。偶而，有的半导体厂家把SOP 归为 SMD(见SOP)。

63、 SO(small out-line)
SOP 的别称。世界上很多半导体厂家都采用此别称。(见SOP)。

64、SOI(small out-line I-leaded package)
I 形引脚小外型封装。表面贴装型封装之一。引脚从封装双侧引出向下呈 I 字形，中心距 1.27mm。贴装占有面积小于SOP。日立公司在模拟 IC(电机驱动用IC)中采用了此封装。引脚数26。

65、SOIC(small out-line integrated circuit)
SOP 的别称( 见SOP)。国外有许多半导体厂家采用此名称。

66、SOJ(Small Out-Line J-Leaded Package)
J 形引脚小外型封装。表面贴装型封装之一。引脚从封装两侧引出向下呈J 字形，故此得名。通常为塑料制品，多数用于 DRAM 和SRAM 等存储器LSI 电路，但绝大部分是DRAM 。用SOJ封装的DRAM 器件很多都装配在SIMM 上。引脚中心距1.27mm，引脚数从20 至40( 见SIMM)。

67、SQL(Small Out-Line L-leaded package)
按照JEDEC(美国联合电子设备工程委员会)标准对SOP 所采用的名称(见SOP)。

68 、SONF(Small Out-Line Non-Fin)
无散热片的SOP。与通常的SOP 相同。为了在功率IC 封装中表示无散热片的区别，有意增添了NF(non-fin)标记。部分半导体厂家采用的名称 (见SOP)。

69、 SOF(small Out-Line package)
小外形封装。表面贴装型封装之一，引脚从封装两侧引出呈海鸥翼状(L 字形) 。材料有塑料和陶瓷两种。另外也叫SOL 和DFP。SOP 除了用于存储器LSI 外，也广泛用于规模不太大的ASSP 等电路。在输入输出端子不超过 10～40 的领域，SOP 是普及最广的表面贴装封装。引脚中心距 1.27mm，引脚数从8～44。另外，引脚中心距小于1.27mm 的SOP 也称为SSOP ；装配高度不到1.27mm 的SOP 也称为 TSOP( 见SSOP、TSOP)。还有一种带有散热片的SOP。

70、SOW (Small Outline Package(Wide-Jype))
宽体SOP 。部分半导体厂家采用的名称。

Ebook--Low Power Methodology Manual[printable]

2007-12-11T23:29:00.001+08:00

Ebook share, Thanks to visit my blog!
Low Power MethodologyManual For System-on-Chip Design.
sorry, I can not share this book for some jural reason.
if you are interesting with this book, you can refer http://www.synopsys.com/partners/arm/lpmm/lpmm.html

ECO Flow[By Nir Dahan]

2007-12-06T09:23:00.001+08:00

    I have posted a blog about ECO some monthes ago, see http://www.yanzhi.org/blog/2007/04/eco.html
    And now it's another eco post from: Adventures in ASIC Digital Design , just for reference.

ECO Flow    By Nir Dahan

Here is a useful checklist you should use when doing your ECOs.
   1. RTL bug fix
      Correct your bug in RTL, run simulations for the specific test cases and some your general golden tests. See if you corrected the problem and more important didn't destroy any correct behavior.
   2. Implement ECO in Synthesis netlist
      Using your spare cells and/or rewiring, implement the bug fix directly in the synthesis verilog netlist. Remember you do not re-synthesize the entire design, you are patching it locally.
   3. Run equivalence check between synthesis and RTL
      Using your favorite or available formal verification tool, run an equivalence check to see if the code you corrected really translates to the netlist you patched. Putting it simply - the formal verification tool runs through the entire state space and tries to look for an input vector that will create 2 different states in the RTL code and the synthesis netlist. If the two designs are equivalent you are sure that your RTL simulations would also have the same result (logically speaking) as the synthesis netlist.
   4. Implement ECO in layout netlist
      You will now have to patch your layout netlist as well. Notice that this netlist is very different than the synthesis netlist. It usually has extra buffers inserted for edge shaping or hold violation correction or maybe even totally differently logically optimized.
      This is the real thing, a change here has to take into account the actual position of the cells, the actuall names etc. Try to work with the layout expert in close proximity. Make sure you know and understand the floorplan as well - it is very common to connect a logic gate which is on the other side of the chip just because it is logically correct, but in reality it will violate timing requirements.
   5. Run equivalence check between layout and synthesis
      This is to make sure the changes you made in the layout netlist are logically equivalent to the synthesis. Some tools and company internal flows enable a direct comparison of the layout netlist to the RTL. In many it is not so and one has to go through the synthesis netlist change as well
   6. Layout to GDS / gate level simulations / STA runs on layout netlist (all that backend stuff…)
      Let the layout guys do their magic. As a designer you are usually not involved in this step.
      However, depending on your timing closure requirements, run STA on the layout netlist to see if everything is still ok. This step might be the most crucial since even a very small change might create huge timing violations and you would have to redo your work.
      Gate level simulations are also recommended, depending on your application and internal flow.

What is the difference between hard macro, firm macro and soft macro?

2007-12-01T09:53:00.001+08:00

From http://vlsifaq.blogspot.com/ By murali

What are IPs?

Hard macro, firm macro and soft macro are all known as IP (Intellectual property). They are optimized for power, area and performance. They can be purchased and used in your ASIC or FPGA design implementation flow. Soft macro is flexible for all type of ASIC implementation. Hard macro can be used in pure ASIC design flow, not in FPGA flow. Before bying any IP it is very important to evaluate its advantages and disadvantages over each other, hardware compatibility such as I/O standards with your design blocks, reusability for other designs.

Soft macros

Soft macros are in synthesizable RTL.

Soft macros are more flexible than firm or hard macros.

Soft macros are not specific to any manufacturing process.

Soft macros have the disadvantage of being somewhat unpredictable in terms of performance, timing, area, or power.

Soft macros carry greater IP protection risks because RTL source code is more portable and therefore, less easily protected than either a netlist or physical layout data.

From the physical design perspective, soft macro is any cell that has been placed and routed in a placement and routing tool such as Astro. (This is the definition given in Astro Rail user manual !)

Soft macros are editable and can contain standard cells, hard macros, or other soft macros.

Firm macros

Firm macros are in netlist format.

Firm macros are optimized for performance/area/power using a specific fabrication technology.

Firm macros are more flexible and portable than hard macros.

Firm macros are predictive of performance and area than soft macros.

Hard macro

Hard macros are generally in the form of hardware IPs (or we termed it as hardwre IPs !).

Hard macos are targeted for specific IC manufacturing technology.

Hard macros are block level designs which are silicon tested and proved.

Hard macros have been optimized for power or area or timing.

In physical design you can only access pins of hard macros unlike soft macros which allows us to manipulate in different way.

You have freedom to move, rotate, flip but you can't touch anything inside hard macros.

Very common example of hard macro is memory. It can be any design which carries dedicated single functionality (in general).. for example it can be a MP4 decoder.

Be aware of features and characteristics of hard macro before you use it in your design... other than power, timing and area you also should know pin properties like sync pin, I/O standards etc

LEF, GDS2 file format allows easy usage of macros in different tools.

From the physical design (backend) perspective:

Hard macro is a block that is generated in a methodology other than place and route (i.e. using full custom design methodology) and is brought into the physical design database (eg. Milkyway in Synopsys; Volcano in Magma) as a GDS2 file.

Here is one article published in embedded magazine about IPs. Click here to read.

Synthesis and placement of macros in modern SoC designs are challenging. EDA tools employ different algorithms accomplish this task along with the target of power and area. There are several research papers available on these subjects. Some of them can be downloaded from the given link below.

"Hard Macro Placement in Complex SoC Design" - view and read article from soccentral

"Hard Macro Placement in Complex SoC Design" - download white paper

IEEE/Univerity research papers

"Local Search for Final Placement in VLSI Design" - download

"Consistent Placement of Macro-Blocks Using Floorplanning and standard cell placement" - download

"A Timing-Driven Soft-Macro Placement And Resynthesis Method In Interaction with Chip Floorplanning" - download

Physical Design Flow

2007-11-21T13:23:00.000+08:00

from ASIC-System On Chip (SoC)-VLSI Design by murali

删除文本文件中包含特定字符串所在行[script tips]

2007-11-21T10:01:00.001+08:00

grep
-v, --invert-match select non-matching lines
grep -v "string" tee tmp.file
mv -f tmp.file original.file
or
vi
:g/string/d

[转]What is the difference between FPGA and ASIC?

2007-11-20T16:25:00.001+08:00

from VLSI Interview Questions by murali

This question is very popular in VLSI fresher interviews. It looks simple but a deeper insight into the subject reveals the fact that there are lot of thinks to be understood !! So here is the answer.

FPGA vs. ASIC

Difference between ASICs and FPGAs mainly depends on costs, tool availability, performance and design flexibility. They have their own pros and cons but it is designers responsibility to find the advantages of the each and use either FPGA or ASIC for the product. However, recent developments in the FPGA domain are narrowing down the benefits of the ASICs.

FPGA

Field Programable Gate Arrays

FPGA Design Advantages

Faster time-to-market: No layout, masks or other manufacturing steps are needed for FPGA design. Readymade FPGA is available and burn your HDL code to FPGA ! Done !!

No NRE (Non Recurring Expenses): This cost is typically associated with an ASIC design. For FPGA this is not there. FPGA tools are cheap. (sometimes its free ! You need to buy FPGA.... thats all !). ASIC youpay huge NRE and tools are expensive. I would say "very expensive"...Its in crores....!!

Simpler design cycle: This is due to software that handles much of the routing, placement, and timing. Manual intervention is less.The FPGA design flow eliminates the complex and time-consuming floorplanning, place and route, timing analysis.

More predictable project cycle: The FPGA design flow eliminates potential re-spins, wafer capacities, etc of the project since the design logic is already synthesized and verified in FPGA device.

Field Reprogramability: A new bitstream ( i.e. your program) can be uploaded remotely, instantly. FPGA can be reprogrammed in a snap while an ASIC can take $50,000 and more than 4-6 weeks to make the same changes. FPGA costs start from a couple of dollars to several hundreds or more depending on the hardware features.

Reusability: Reusability of FPGA is the main advantage. Prototype of the design can be implemented on FPGA which could be verified for almost accurate results so that it can be implemented on an ASIC. Ifdesign has faults change the HDL code, generate bit stream, program to FPGA and test again.Modern FPGAs are reconfigurable both partially and dynamically.

FPGAs are good for prototyping and limited production.If you are going to make 100-200 boards it isn't worth to make an ASIC.

Generally FPGAs are used for lower speed, lower complexity and lower volume designs.But today's FPGAs even run at 500 MHz with superior performance. With unprecedented logic density increases and a host of other features, such as embedded processors, DSP blocks, clocking, and high-speed serial at ever lower price, FPGAs are suitable for almost any type of design.

Unlike ASICs, FPGA's have special hardwares such as Block-RAM, DCM modules, MACs, memories and highspeed I/O, embedded CPU etc inbuilt, which can be used to get better performace. Modern FPGAs are packed with features. Advanced FPGAs usually come with phase-locked loops, low-voltage differential signal, clock data recovery, more internal routing, high speed, hardware multipliers for DSPs, memory,programmable I/O, IP cores and microprocessor cores. Remember Power PC (hardcore) and Microblaze (softcore) in Xilinx and ARM (hardcore) and Nios(softcore) in Altera. There are FPGAs available now with built in ADC ! Using all these features designers can build a system on a chip. Now, dou yo really need an ASIC ?

FPGA sythesis is much more easier than ASIC.

In FPGA you need not do floor-planning, tool can do it efficiently. In ASIC you have do it.

FPGA Design Disadvantages

Powe consumption in FPGA is more. You don't have any control over the power optimization. This is where ASIC wins the race !

You have to use the resources available in the FPGA. Thus FPGA limits the design size.

Good for low quantity production. As quantity increases cost per product increases compared to the ASIC implementation.

ASIC

Application Specific Intergrated Circiut

ASIC Design Advantages

Cost....cost....cost....Lower unit costs: For very high volume designs costs comes out to be very less. Larger volumes of ASIC design proves to be cheaper than implementing design using FPGA.

Speed...speed...speed....ASICs are faster than FPGA: ASIC gives design flexibility. This gives enoromous opportunity for speed optimizations.

Low power....Low power....Low power: ASIC can be optimized for required low power. There are several low power techniques such as power gating, clock gating, multi vt cell libraries, pipelining etc are available to achieve the power target. This is where FPGA fails badly !!! Can you think of a cell phone which has to be charged for every call.....never.....low power ASICs helps battery live longer life !!

In ASIC you can implement analog circuit, mixed signal designs. This is generally not possible in FPGA.

In ASIC DFT (Design For Test) is inserted. In FPGA DFT is not carried out (rather for FPGA no need of DFT !) .

ASIC Design Diadvantages

Time-to-market: Some large ASICs can take a year or more to design. A good way to shorten development time is to make prototypes using FPGAs and then switch to an ASIC.

Design Issues: In ASIC you should take care of DFM issues, Signal Integrity isuues and many more. In FPGA you don't have all these because ASIC designer takes care of all these. ( Don't forget FPGA isan IC and designed by ASIC design enginner !!)

Expensive Tools: ASIC design tools are very much expensive. You spend a huge amount of NRE.

Structured ASICS

Structured ASICs have the bottom metal layers fixed and only the top layers can be designed by the customer.

Structured ASICs are custom devices that approach the performance of today's Standard Cell ASIC while dramatically simplifying the design complexity.

Structured ASICs offer designers a set of devices with specific, customizable metal layers along with predefined metal layers, which can contain the underlying pattern of logic cells, memory, and I/O.

FPGA vs. ASIC Design Flow Comparison

http://www.xilinx.com/company/gettingstarted/fpgavsasic.htm

a new gmail account for file sharing

2007-11-14T23:21:00.001+08:00

I have created a email account[gmail file sytem] for file sharing.

account: share@ipcoretech.com

password: ipcoretech.com

address: http://mail.ipcoretech.com

I have uploaded the "gmail driver" in it,and everyone can login and download it.

Everyone can use this account by gmail dirver[maybe windows only] for sharing your files.

Google搜索在工作上的应用技巧[ 转]

2007-11-10T11:10:00.001+08:00

转自：http://www.williamlong.info/archives/572.html

Google良好的搜索和易用性已经得到了广大网友的欢迎，但是除了我们经常使用的Google网站、图像和新闻搜索之外，它还有很多其他搜索功能和搜索技巧。如果我们也能充分利用，必将带来更大的便利。这里我介绍几个很有用的搜索技巧，在平时搜索中可以结合使用。

　　一、限定搜索范围的技巧

　　1、文件类型

　　有时候我们可能不需要搜索网页文件或者图片，我们可能想要搜索其他类型的问题，比如文档文件（Word，Excel，PPT），Flash文件，甚至是Google地图文件，我们都可以使用"filetype"功能来实现。

　　比如我想搜索一篇关于最新加密技术的Word论文，使用Google搜索"filetype:doc 加密技术 "即可得到大量相关信息。我想搜索关于中国的Google Earth卫星图片，那么就在Google中搜索"filetype:kmz china"即可。

　　2、指定网站

　　有时我们进行网页搜索，想要在某一个指定的网站内搜索感兴趣的内容，这时候我们可以使用"site"功能来限定搜索的网站。

　　比如，我想在新浪网上搜索关于世界杯赛程的消息，只需要用Google搜索"site:sina.com.cn 世界杯赛程"即可得到结果。

　　如果你想把搜索结果限制在大学的网站之中，可以使用"site:.edu 关键词"。

　　通过限定搜索范围的方法，我们可以更快更准确的搜索到我们想要的东西。

　　3、其他限定搜索方法

　　intitle：搜索关键词（intitle:关键字）只搜索网页标题含有关键词的页面。

　　inurl：搜索关键词（intitle:关键字）只搜索网页链接含有关键词的页面。

　　intext：搜索关键词（intext:关键字）只搜索网页body标签中的文本含有关键词的页面。

　　二、写作辅助小工具

　　Google有一些小工具，为我们的日常工作学习提供了很多方便之处。

　　1、翻译工具

　　Google本身带有中英文翻译的功能，只需输入一个关键词("翻译"或"fy"任选其一）和要查的中（英）文单词，Google会直接显示您要查的单词的英文（或中文）翻译。

　　比如我们想要翻译"香蕉"这个词为英文，那么只需要在Google中搜索"翻译香蕉"或者"fy 香蕉"，返回的第一条记录就是翻译的结果。同样，我们搜索"fy banana"可以得到这个单词的中文翻译。

　　2、学术词典工具

　　我们有时候想要知道一个具体词汇的定义，可以使用"定义"或"define"，接着键入一个空格，然后键入您需要其定义的词。

　　比如，我们想要知道氨基酸是什么意思，只需要在Google中搜索"定义氨基酸"，就可以找到氨基酸的定义。

　　三、改进工作效率

　　做为一个公司员工，每天都要关注自己公司和竞争对手的最新消息，怎么才能在最短的时间内获得最多的信息呢？Google可以帮助你。

　　Google 快讯是Google的新闻定制自动发送，用户可以定制自己需要的内容，Google会在设定的时间内（即时、每天、每周）给用户发送Google最新搜索到的新闻文章，非常方便，我们就可以用这个功能来跟踪自己公司和竞争对手的最新消息。

　　例如我是一家做搜索的开发公司，我需要每天关注自己的竞争对手，因此我只要登录：http://www.google.com/alerts?hl=zh-CN，然后在"搜索字词"中输入"Google"，"频率"为每天，即可每天收到关于Google的最新消息，同样在"搜索字词"中输入"百度"，可以获得百度的最新消息。

　　当然，搜索关键字不只是公司，开动我们的脑筋，我们可以用这个工具跟踪任何信息，比如输入某个名人的名字，可以追踪这个名人的最新消息和新闻，搜索某个行业名称，可以追踪这个行业的相关新闻，搜索某个新闻事件，可以得到这个事件的最新报道。

　　因此，我们只要灵活掌握和运行Google的搜索技巧，那会给自己的工作和学习带来相当大的提升，使得自己的事业能够更上一层楼。

blog backup

2007-11-06T20:31:00.000+08:00

没能找到快捷的办法直接从那个blog直接导入到这里，只好一篇篇手工copy，终于把http://www.yanzhi.org/blog/的文章copy过来了，这里仅此是作为它的一个备份，因为那边经常出现不能正常访问的情况，而且在国外访问速度较慢。
但由于blogspot在国内随时有着被封的危险，故还是以自己的虚拟主机空间为主体。
此后所有更新在两边同步进行。
http://www.yanzhi.org/blog/
http://digital-ic-design.blogspot.com/

Some Testing Glossary

2007-11-06T20:30:00.001+08:00

[From http://digitalelectronics.blogspot.com/2007/10/some-testing-glossary.html ]

Black box testing

not based on any knowledge of internal design or code. Tests are based on requirements and functionality.

White box testing

based on knowledge of the internal logic of an application's code. Tests are based on coverage of code statements, branches, paths, conditions.

Unit testing

the most 'micro' scale of testing; to test particular functions or code modules. Typically done by the programmer and not by testers, as it requires detailed knowledge of the internal program design and code. Not always easily done unless the application has a well-designed architecture with tight code; may require developing test driver modules or test harnesses.

Incremental integration testing

continuous testing of an application as new functionality is added; requires that various aspects of an application's functionality be independent enough to work separately before all parts of the program are completed, or that test drivers be developed as needed; done by programmers or by testers.

Integration testing

testing of combined parts of an application to determine if they function together correctly. The 'parts' can be code modules, individual applications, client and server applications on a network, etc. This type of testing is especially relevant to client/server and distributed systems.

Functional testing

black-box type testing geared to functional requirements of an application; this type of testing should be done by testers. This doesn't mean that the programmers shouldn't check that their code works before releasing it (which of course applies to any stage of testing.)

System testing

black box type testing that is based on overall requirement specifications; covers all combined parts of a system.

End-to-end testing

similar to system testing; the 'macro' end of the test scale; involves testing of a complete application environment in a situation that mimics real-world use, such as interacting with a database, using network communications, or interacting with other hardware, applications, or systems if appropriate.

Sanity testing

typically an initial testing effort to determine if a new software version is performing well enough to accept it for a major testing effort. For example, if the new software is crashing systems every 5 minutes, bogging down systems to a crawl, or destroying databases, the software may not be in a 'sane' enough condition to warrant further testing in its current state.

Regression testing

re-testing after fixes or modifications of the software or its environment. It can be difficult to determine how much re-testing is needed, especially near the end of the development cycle. Automated testing tools can be especially useful for this type of testing.

Acceptance testing

final testing based on specifications of the end-user or customer, or based on use by end-users/customers over some limited period of time.

Load testing

testing an application under heavy loads, such as testing of a web site under a range of loads to determine at what point the systems response time degrades or fails.

Stress testing

term often used interchangeably with 'load' and 'performance' testing. Also used to describe such tests as system functional testing while under unusually heavy loads, heavy repetition of certain actions or inputs, input of large numerical values, large complex queries to a database system, etc.

Performance testing

term often used interchangeably with 'stress' and 'load' testing. Ideally 'performance' testing (and any other 'type' of testing) is defined in requirements documentation or QA or Test Plans.

Usability testing

testing for 'user-friendliness'. Clearly this is subjective, and will depend on the targeted end-user or customer. User interviews, surveys, video recording of user sessions, and other techniques can be used. Programmers and testers are usually not appropriate as usability testers.

Install/uninstall testing

testing of full, partial, or upgrade install/uninstall processes.

Recovery testing

testing how well a system recovers from crashes, hardware failures, or other catastrophic problems.

Security testing

testing how well the system protects against unauthorized internal or external access, willful damage, etc; may require sophisticated testing techniques.

Compatibility testing

testing how well software performs in a particular hardware/software/operating system/network/etc. environment.

Exploratory testing

often taken to mean a creative, informal software test that is not based on formal test plans or test cases; testers may be learning the software as they test it.

Ad-hoc testing

similar to exploratory testing, but often taken to mean that the testers have significant understanding of the software before testing it.

User acceptance testing

determining if software is satisfactory to an end-user or customer.

Comparison testing

comparing software weaknesses and strengths to competing products.

Alpha testing

testing of an application when development is nearing completion; minor design changes may still be made as a result of such testing. Typically done by end-users or others, not by programmers or testers.

Beta testing

testing when development and testing are essentially completed and final bugs and problems need to be found before final release. Typically done by end-users or others, not by programmers or testers.

Mutation testing

a method for determining if a set of test data or test cases is useful, by deliberately introducing various code changes ('bugs') and retesting with the original test data/cases to determine if the 'bugs' are detected. Proper implementation requires large computational resources.

set false path

2007-11-06T20:29:00.003+08:00

A mistake in my work:
In the synthesis script, we use the script below to set false path between each clock.
set _all_clks [all_clocks];
foreach_in_collection _clk $_all_clks {
foreach_in_collection _other_clk [remove_from_collection $_all_clks $_clk] {
set_false_path -from $_clk -to $_other_clk;
}
}
However, there are two clocks with the same source(frenquence&phase) but different clock gatin cell , and we think they are the same in the design. So we need reset them.
reset_path -from A_CLK -to B_CLK;
reset_path -from B_CLK -to A_CLK;

Query Yourself before Architecting a Chip

2007-11-06T20:29:00.001+08:00

[From:http://www.vlsichipdesign.com/askyourselfarchitect.html]
This article assuming you are an Architect and What all questions will come to your thought process before Architecting and making the Chip as a first-pass success. Chip Design is an Integration Challenge.

What is the targetted market for this Chip.
What are the competitor's to this Chip and Market Requirement and ROI
What is the Fabrication Unit the Chip is targetted for?
What is the Success rate and Yield numbers achieved in the Fabrication Unit
What is the technology Process targetted for
What is the correlation of the library models w.r.t. Silicon
What are the various Protocols the Chip is going to address
Hardware & Software Parti-tioning.
What is the processor/micro-controller suitable for this application.
What is the bus-architecture targetted
What is the performance targets for this bus architecture
What are the various Interfaces the Chip is having
Is the design going to be in single Vt or with Multi-Vt design
Is using Embedded macro's right choice or Memory Macros
What are the IP's are going to be Re-usued
What are the IP's going to Hard-macro's
What is the Verification Status and corner-case coverage of the I.P's
What is the Die-size targetted/Estimated for the Chip
What is the Power targets
Is Power Management Unit a requirement in the chip to reduce Dynamic power
What are the mechanisms followed to reduce the leakage power
Is Module enables/clock-gating a part of the Methodology
Is resets going to synchronous or asynchronous
What are the various Synchronous Mechanisms for data-transfer's
How many clock-domains required for the Chip
How many PLL's are required or single PLL sufficient for all the clocks required
What is the thought process behind PAD's Is LVTTL/SSTL pads
Is the package going to wire-bond or Flip-chip
Methodology for Optimal Power-grid design
What are the noise reducing Mechanism's in case of analog integration
Is there any requirement of speed monitor's or process checking blocks
What is the type of fuses used laser fuse or efuses
Is there any requirement of Fib Cells in the Design
What are the mechanism's used to handle ESD
what is the reliability target of the Chip and how it is addressed
What are the Mechanisms used for Yield improvement
Is the chip tested at at-speed test
How much Memory-map is allocated for the IP's
What is the metric for spare-gates in the Chip for ECO's
Is repairable memories required
What is the tester targetted and the requirement to the Chip in terms of Scan-chain
Is test-vector compression mechanism's a requirement
What is the PLL performance in terms of Jitter
What is the Interrupt handling mechanism with in the Chip.
What is the ROM-Code for the Chip.
What is the Chip utilization targets
Will the chip be routable or any requirement for special libraries with different routing tracks.
What is the Methodology for tools and versions
What is the Version control mechanism planned for data handling across multi Geographical Environments.
What is the signoff criteria for the Chip
What is the frequency targets for the Chip.
Is there room for further revisions of the Chip.
If the Chip has DDR/SDR interface is there any requirement for DLL.
What are the limitations of the Tools interms of Complexity/run-times/turn-around times/Computation Power requirements.
What is the Mechanisms/Steps taken for the various Variabilities in the Chip IR drop/Power ground noise/inductance effects/EMI noise/Package noise/Crosstalk noise/Simultaneous Switching noise/Channel length variation/On chip Variation/Inter die variations/Intra die Process variations.

On-Chip Variation(OCV) Analysis

2007-11-06T20:28:00.001+08:00

On Chip Variations or inter-die variations could be caused due to :
• IR drop
• Vt variations
• Channel length variation
So the normal flow of qualifying the Timing with plain worst and best corners is no more enough.

Performing On-Chip Variation Analysis[From PrimeTime UG]
To perform on-chip variation analysis, use the set_operating_conditions command.
Because on-chip variations consider that cells and nets can operate at slightly different operating conditions, you must consider a minimum value and a maximum value for each delay of the design.Specify two operating conditions to represent the lower and upper bounds of the operating condition for on-chip variation, keeping the following guidelines in mind.
• Each delay of the design has an uncertainty bounded by the minimum value (computed for the minimum operating condition) and maximum value (computed for the maximum operating condition).
• Minimum paths are computed using the delay of the minimum operating condition.
• Maximum paths are computed using the delay of the maximum operating condition.

Example 1
This command sequence performs timing analysis for on-chip variation 20 percent below the worst-case commercial (WCCOM)
operating condition. It also performs clock reconvergence pessimism removal for paths with positive slack.
pt_shell> set_operating_conditions -analysis_type on_chip_variation WCCOM
pt_shell> set_timing_derate -min 0.8 -max 1.0

pt_shell> report_timing -remove_clock_reconvergence_pessimism 0.0
Example 2
This command sequence performs timing analysis for on-chip variation between two predefined operating conditions:WCCOM_scaled andWCCOM.It also performsclock reconvergence pessimism removal for paths with slack less than 0.4 ns.
pt_shell> set_operating_conditions -analysis_type on_chip_variation \
? -min WCCOM_scaled -max WCCOM
pt_shell> report_timing -remove_clock_reconvergence_pessimism 0.4
Example 3
This command sequence performs timing analysis for on-chip variation 5 percent above and 10 percent below the SDF backannotated
cell delays. For net delays, the on-chip variation is between 2 percent above and 4 percent belowtheSDFback-annotated values.
For timing delays, the on-chip variation for timing checks is 10 percent above the SDF values for setup and 20 percent belowthe SDF values for hold checks.
pt_shell> read_sdf -analysis_type on_chip_variation my_design.sdf
pt_shell> set_timing_derate -cell -min 0.90 -max 1.05
pt_shell> set_timing_derate -net -min 0.96 -max 1.02
pt_shell> set_timing_derate -cell_check -min 0.80 -max 1.10

Synopsys Design Compiler-A quick Tutorial

2007-11-06T20:27:00.000+08:00

From: http://www.vlsiip.com/dc_shell/

Step 0. Invoke Design Compiler
unix> dc_shell-t
Step 1. Setup technology library. To synthesize a design you need technology library which will contain
description of the cells from the fab, and their timing. This is usually a .db file found in
library installation directory. To do this
1(a). Tell synopsys where your <library>.db file is.
set search_path {/homes/amittal/s5/work/physical_lib/corelib/tsmc_090_g_art}
1(b). Tell synopsys what is your technology library, which you want to map your design on called
set target_library {scadv_tsmc_cln90g_lvt_ss_0p9v_125c.db}
1(c). Set up link libraries. This is optional .db files which are pre synthesized and ready to be read in
For this, append your search path where your optional .db files are
lappend search_path {[exec pwd]}
lappend search_path {.}
1(d). Set up link libraries. This is optional .db files which are pre synthesized and ready to be read in
set link_library {PLL10CCMID_W_125_1.35.db}
Step 2. Read In your design files
2(a). if it is verilog:
read_verilog counter.v
2(b). if it is vhdl: As it is in this tutorial
read_vhdl counter.vhd
read_vhdl counter_top.vhd
2(c). if it is ddc:
read_ddc counter.ddc
Step 3. Set Design Constraints:
3(a) Set frequency of operation: You have to create a clock in the design,
With a given timeperiod. The command below creates a clock and calls it
'design_clk' with a timeperiod of 10 ns, (100MHz), and maps it to the
'clk' input of the design.
create_clock -period 10 -name design_clk clk
3(b) Set input constraints : Set how much time would be spent by
signals arriving into your design, outside your design with respect to the clock
set_input_delay 4.0 [remove_from_collection [all_inputs ] clk] -clock design_clk
3(c) Set output constraints : Set how much time would be spent by
signals leaving your desing, outside your design, before they are captured by
the same clock
set_output_delay 7.0 [all_outputs] -clock design_clk
3(d) Set area constraints : set maximum allowed area to 0 :). well its just to
instruct design compiler that use as less area as possible.
set_max_area 0
Step 4. Enable clock gating for low power (optional)
4(a) The following commands will try to insert clock gates for each 2 registers
set_clock_gating_style -minimum_bitwidth 2
Step 5. Write formal verification setupfile (optional)
set_svf -append "counter.svf"
Step 6. Set Register optimization veriables (optional)
(a) Set automatic removal of constant flipflop(s)
set compile_seqmap_propagate_constants true
(b) Set automatic removal of unloaded flipflop(s)
set compile_delete_unloaded_sequential_cells false
Step 7. Set mapping of sync resets to aviod Xs in sims (optional)
set hdlin_ff_always_sync_set_reset "true"
Step 8. Set the name of top level as current design and compile the design
(a) current_design counter_top
compile -map_effort high
(b) If you are using dc ultra :
compile_ultra
You may want to turn off output inversion of sequential cells
compile_ultra -no_seq_output_inversion
Step 9. Write design output netlist
9(a).Write output in ddc format
write -format ddc -output counter.ddc -hier
9(b).Write output in verilog format
write -format ddc -output counter.vlog -hier
Step 10. You may want to flatten your design before writing out netlist
ungroup -all -flatten
write -format verilog -output counter_flat.vlog
Step 11. Writing a timing report of your design
report_timing > counter_timing.rep
Step 12. Quit Design Compiler
quit

More random DC shell Tcl mode Commands:

define_design_lib lib1 -path ~/misc/vhdl
analyze -library lib1 -format vhdl /homes/amittal/misc/vhdl/xx.vhdl
get_design_lib_path SYNTH
get_design_lib_path work

read_verilog mse.v

report_timing -delay max -from ARRAYCACHE_I/CACHEDIRRAM_I/regfile64x704_assembly_0/RA_ram[3] -to pCacheMemReqFifoDataOut

report_timing -delay max -through [find net ARRAYCACHE_I/CACHEDIRRAM_I/regfile64x704_assembly_0/RA_ram[3]]

report_constraint -verbose -all_violators

create_clock -name "myclk" -period 13 [get_ports pClk]

set_output_delay 1.0 -clock [get_clocks myclk] pCacheMemReqFifoDataOut[161]

set_wire_load_mode segmented

set_wire_load_mode enclosed

update_timing

report_timing -from [find pin ARRAYCACHE_I/LatencyReqReg*/Q] -to pCacheMemReqFifoDataOut

report_timing -from [find pin ARRAYCACHE_I/CACHE_DATA_RAM/DO*] -to pCacheMemReqFifoDataOut

set_output_delay 1.0 -clock myclk pCacheMemReqFifoDataOut

set_false_path -through [find pin ARRAYCACHE_I/FracSetReg*/*]index

It is to be noted that if there are no constraints, 'set_false_path' does not actually works.

I tried to find delays to a output port, without any constraints, form a known point in the design.
I got that.
Then I wanted to find next worst path to that output port, to I set a false path on the path found above.
But it wouldn't work
I then created a clcok and constrainted the output port,
!! False path worked.... magic :)

create_clock -period 4.8 -name vclk
set_input_delay 2.5 pDmaReadRegIndex -clock vclk -add_delay
set_output_delay 2.5 pInsertNopOut -clock vclk -add_delay
set_false_path -from vclk -to PESWITCH_pClk
set_false_path -from PESWITCH_pClk -to vclk
set_false_path -from PESWITCH_pClk -through pDmaReadRegIndex -to pInsertNopOut
report_timing -from pDmaReadRegIndex -to pInsertNopOut

set_input_delay [expr 0.35*$vclk_period] [all_inputs] -clock vclk -add_delay
set_output_delay [expr 0.35*$vclk_period] [all_outputs] -clock vclk -add_delay
set_false_path -from PESWITCH_pClk -through [all_inputs] -to [all_outputs]

set compile_log_format "%elap_time %area %wns %tns %drc %endpoint %group_path"

Handle Unconnected Pins in Design Compiler

2007-11-06T20:26:00.000+08:00

Question:

The original Verilog code snippet is as follows:
module sub ( C, z );
input C;
output z;
AN3 U1 ( .A(), .B(), .C(C), .Z(z) );
endmodule
In the dumped Verilog, the code is as follows:
module sub ( C, z );
input C;
output z;
AN3 U1 ( .A(1'b0), .B(1'b0), .C(C), .Z(z) );
endmodule
Why does Design Compiler connect unconnected pins to 0?

Answer:

Because Design Compiler does not allow a floating input of a cell, an
unconnected input will always be tied to '0' or '1'.
So in the dumped Verilog, you can see the unconnected pin A connected to 0,
But from version Z-2007.03-SP1, the behavior is different. Check the dumped
Verilog; it is similar to the following:
=============================
wire net1, net2;
MUX2D1 U1 ( .I0(net1), .I1(net2),.C(C), .Z(z) );
Notice the difference in the generated Verilog between versions
Y-2006.06 and Z-2007.03.

Wire Load Model

2007-11-06T20:25:00.002+08:00

Defining Wire Load Models
Wire load modeling allows you to estimate the effect of wire length and fanout on the resistance, capacitance, and area of nets. Design Compiler uses these physical values to calculate wire delays and circuit speeds. Semiconductor vendors develop wire load models, based on statistical information specific to the vendors' process. The models
include coefficients for area, capacitance, and resistance per unit length, and a fanout-to-length table for estimating net lengths (the number of fanouts determines a nominal length).
Note:
You can also develop custom wire load models.

Wire load models estimate the effect of wire length on design performance. It should be speicfied when define the design environment.

Determining Available Wire Load Models
Use the report_lib command to list the wire load models defined in a technology library. The library must be loaded in memory before you run the report_lib command.
eg:
dc_shell-xg-t> read_file my_lib.db

Example Wire Load Models Report
****************************************
Report : library
Library: my_lib
Version: Y-2006.06
Date : Mon May 1 10:56:49 2006
****************************************
...
Wire Loading Model:
Name : 05x05
Location : my_lib
Resistance : 0
Capacitance : 1
Area : 0
Slope : 0.186
Fanout Length Points Average Cap Std Deviation
------------------------------------------------------------------------
1 0.39

Name : 10x10
Location : my_lib
Resistance : 0
Capacitance : 1
Area : 0
Slope : 0.311
Fanout Length Points Average Cap Std Deviation
------------------------------------------------------------------------
1 0.53
...

Specifying Wire Load Models and Modes
The default_wire_load library attribute identifies the default wire load model for a technology library.To change the wire load model or mode specified in a technology library, use the set_wire_load_model and set_wire_load_mode commands.
eg:
dc_shell-xg-t> set_wire_load_model "10x10"
dc_shell-xg-t> set_wire_load_mode enclosed

If you need more detail infomation about wire_load_model,please refer the Design Compiler Usage.

Why we should do gate-level simulation?[转]

2007-11-06T20:25:00.001+08:00

From http://blog.dicder.com/html/3/3-287.html

SNUG:All My X's Come From Texas…Not!!
Matt Weber
Jason Pecor
Silicon Logic Engineering
In a recent ESNUG article ( http://www.deepchip.com/items/0421-01.html), eighteen engineers shared their view of the current usefulness of gate level simulation. Only one of those engineers has completely removed gate level simulation from their design flow. The other engineers listed many reasons for continuing to do some level of gate level simulation.
1. Since scan and other test structures are added during and after synthesis, they are not checked by the rtl simulations and therefore need to be verified by gate level simulation.
2. Static timing analysis tools do not check asynchronous interfaces, so gate level simulation is required to look at the timing of these interfaces.
3. Careless wildcards in the static timing constraints set false path or mutlicycle path constraints where they don't belong.
4. Design changes, typos, or misunderstanding of the design can lead to incorrect false paths or multicycle paths in the static timing constraints.
5. Using create_clock instead of create_generated_clock leads to incorrect static timing between clock domains.
6. Gate level simulation can be used to collect switching factor data for power estimation.
7. X's in RTL simulation can be optimistic or pessimistic. The best way to verify that the design does not have any unintended dependence on initial conditions is to run gate level simulation.
8. It's a nice "warm fuzzy" that the design has been implemented correctly.

A IPcore Introduction[just as a template]

2007-11-06T20:24:00.000+08:00

BodaHx8 - MPEG-2 MP + H.264 HP + VC-1 AP + MPEG-4 ASP (DivX) + RV8/9/10 + JPEG codec (1920*1080*30)

Overview
Chips&Media's BodaHx8 is a high-performance and optimally-unified multi-standard decoder IP that performs three major decoding functionalities such as H.264, MPEG-2, MPEG-4 (DivX), RV8/9/10, JPEG codec and VC-1 up to HD resolution at 30 frames per second. Under our technologies, BodaHx8 needs ultra low-power and ultra low clock frequency based on Chips&Media's advanced video decoding hardware architecture, while BodaHx8 provides decent flexibility in error concealment, error resilient, and multi-resolution/multiplex decoder control based on exclusively designed video core processor.

Features

Standards Compliance - decoder only

ISO/IEC 14496-10 AVC BP@L4, MP@L4 ,HP@L4.1

ISO/IEC 13818-2 MPEG-2 MP@HL

ISO/IEC 14496-2 MPEG-4 ASP (DivX)

SMPTE VC-1 SP, MP, AP@L3

RV8/9/10

JPEG

Benefits

Interface

Host interface: AMBA3 32-bit APB interface

External memory interface: AMBA3 64-bit AXI Interface or AMBA2 AHB interface

Customized interface for optimally designed bus multi-master environments can be available

Decoding tools

Support all features of the standards

Deblocking filter for post-processing

State-of-art error concealment strategy

Simultaneous multi-standard/multiple decoding is possible

Error resilience tools

Optional: Built-in rotation/mirroring function to remove redundant bus-loading: 90 x n degree rotation (n=0,1,2,3); Vertical/horizontal mirroring

Performance

HD(1920X1080) decoding @ 150MHz

Required host processor resource to run: less than 1 MIPS

Deliverables

RTL source code

IP integration guide & user guide

Test-bench

Evaluation Board

Tech Specs

Part Number	BodaHx8
Short description	MPEG-2 MP + H.264 HP + VC-1 AP + MPEG-4 ASP (DivX) + RV8/9/10 + JPEG codec (1920108030)
Provider:	Chips&Media, Inc
Portability	FPGA
ASIC Target	TSMC@90um
FPGA Target	Xilinx Virtex 4
Type	Soft
Compliant Standard	MPEG-2 MP@HL / MPEG-4 ASP (DivX) / H.264 HP@L4.1 / VC-1 AP@L3.0 / RV8/9/10 / JPEG codec (Full HD decoder)
Maturity	Very good
Availability	Oct, 2007
TSMC Rating :	Verification: 0.09G (CLN90G)
FPGA Technology:	Xilinx: Virtex-4 LX
Bus Compliance :	AMBA AXI

Datasheet:

Related Links:

How Do I Preserve MUX Structures in the Netlist?[from solvnet]

2007-11-06T20:23:00.000+08:00

[I think it's very useful!]
How Do I Preserve MUX Structures in the Netlist?

Question:

I know that I can map the "full case" statements in RTL to MUX_OP synthetic components by using the "infer_mux" synthesis pragma or the "hdlin_infer_mux" global variable. However, in some cases I see that these MUX_OPs are inferred in the GTECH but mapped to non-MUX random logic gates in the library after compile or compile_ultra. How can I preserve these MUX structures even if the QOR is degraded with library MUX cells?

Answer:

If you want Design Compiler to preferentially map multiplexing logic to multiplexers or multiplexer trees in your technology library, you must infer MUX_OP cells. But it doesn't guarantee that the tool will use the MUX from the target library in the final implementation after compile or compile_ultra. Keep in mind that forcing MUXes might degrade the QOR of your design in some cases. So Design Compiler can change MUX_OPs to random logic based on the constraints. Starting from version Z-2007.03-SP3, you can use the set_size_only or set_map_only commands to set size_only or map_only attributes on the MUX_OP cells as follows: -Without size_only and map_only attributes, the MUX_OP synthetic cells are mapped to MUX cells if both area and delay are comparable to equivalent combinational random logic; otherwise combinational random logic is used. -With the map_only attribute, the MUX_OP is initially mapped to MUX cells, but are remapped to combinational random logic if delay can be improved; -With the size_only attribute, the MUX_OP is mapped to MUX cells. The size_only restricts optimization and can result in worse QOR. For example, you can set the attributes as one of the following: set_size_only [get_cells -hier * -filter "@ref_name =~ *MUX_OP*"] or set_map_only [get_cells -hier * -filter "@ref_name =~ *MUX_OP*"] Note: The "set_size_only" solution does not work in versions earlier to Z-2007.03-SP3. The "set_map_only" solution does not work in version earlier to Z-2007.03-SP2.

A good blog for fpga

2007-11-06T20:22:00.002+08:00

FPGA design from scratch

http://svenand.blogdrive.com/

Debussy Trace 2-D register array [tool usage tips]

2007-11-06T20:22:00.001+08:00

In debussy/verdi v5.4 or below, the 2-D register array signal(speified in verilog-2001 syntax) can NOT be traced as usual.
We can add a parameter follow the command to make it support verilog-2001.
eg: verdi -2001 & or debussy -2001 &

reduce run time for postgsim

2007-11-06T20:21:00.000+08:00

When run the post gate level simulation, There usually need be a lone time(maybe several hours or several days for a huge design), so how to reduce the run time is a very useful job.
Firstly, we should analyze where the time consumed? As we know , the tool get the simulation result by calculating all the cell's logical value in the whole simulation process. And, all the process in the synchronous design is based the clock.
So, If we force the clock stop in the sub-design we need not care in the special pattern for the special function.There need be less time to calculate the cell's logical value . For example, we just need verify the video part, we do not need care the audio part, so we can force the clock for audio part on a stable state(gated clock).
It is a very useful method for the large design, specially the well-partitioned design.I use it to save almost the half hours.

Some White Paper for Low-Power

2007-11-06T20:20:00.001+08:00

Low-Power Resources

Whitepaper — "Power Consumption in 65 nm FPGAs" With the introduction of the Xilinx™-5 family, Xilinx is... Read more

Whitepaper — "Power Management In Complex SoC Design" The rise in SoC size and speed, as well as the increase in... Read more

Whitepaper — "Power Integrity for SoCs: Power Planning and Signoff Flows" Power integrity has become a crucial part of... Read more

Whitepaper — "A Practical Methodology for Calculating Acceptable IR Drop Targets in Advanced VDSM Design"

Basic Low Power techniques to reduce Power[转]

2007-11-06T20:19:00.002+08:00

From:http://socdesignsource.org/magicbluesmoke/?p=32
By gmaben

In the process of finding all the advanced techniques to reduce power, we tend to ignore the basic techniques available with the majority of EDA tools. Some of these techniques that are available today and can reduce power to a great extent are :-

(1) Clock gating
(2) Sizing
(3) Factoring
(4) Pin swapping
(5) Inversion Push
(6) Low Power Placement
(7) Register Clustering
(8) Low Power CTS to reduce power in the clock tree
(9) Multi-Vt Optimization to minimize usage of Low Vt cells
(10) Operand Isolation
(11) Data Gating
(12) Bubble Algorithm

These techniques can be enabled by turning on some switches/variables in the Implementation tools. Most of these techniques require representative vector-set. Identifying good representative vectors is a real challenge.

If the vectors are very difficult to access, the best bet would be to enable these techniques once your design meets the required timing/area goals.

We can definitely get an estimate on the average activity factor of various blocks of the design and use these factors to enable low power optimization. This approach can help us in saving power to quite an extent.

For example, I have seen in one of the recent activities, we were able to get around 15-20% power reduction just by enabling Low Power Placement.

ECO小错

2007-11-06T20:19:00.001+08:00

问题：
在定义wire的时候，信号名中带"\"，如wire \CNT[0] ;
不知道是公司的Naming Rule规定的还是Verilog语法规定，在此类信号名的前后必须有一个空格。
但我通过手工输入Command的方式产生的Netlist是不符合这规定的，因此很可能是公司Naming Rule定的。
结论：
在做ECO时手动修改的那部分Netlist一定得符合设计的Naming Rule，此类检查可以通过Debussy的语法检查发现。

google技巧

2007-11-06T20:18:00.001+08:00

在使用DC时，对于初学者来说，很难弄清楚那些具体的综合过程，不过我们可以通过command.log来了解它。
因此，就需要找一个比较好的脚本run过之后的command log来学习。
Google is very powerful！
对于文本文件，我们可以通过约束其扩展名，找到最精确的结果。
如我要找一个command.log的文件，我就可以在搜索栏输入synopsys command filetype:log
对于其他文本文件，也可以采取类似的方式来搜索。
同时，这也是一种不错的逆向学习方法，尤其对于这些EDA工具的学习。

Linux 指令篇:档案目录管理--touch[转]

2007-11-06T20:17:00.000+08:00

名称：touch

使用权限：所有使用者

使用方式：
touch [-acfm]
[-r reference-file] [--file=reference-file]
[-t MMDDhhmm[[CC]YY][.ss]]
[-d time] [--date=time] [--time={atime,access,use,mtime,modify}]
[--no-create] [--help] [--version]
file1 [file2 ...]

说明：
touch 指令改变档案的时间记录。 ls -l 可以显示档案的时间记录。

参数：
a 改变档案的读取时间记录。
m 改变档案的修改时间记录。
c 假如目的档案不存在，不会建立新的档案。与 --no-create 的效果一样。
f 不使用，是为了与其他 unix 系统的相容性而保留。
r 使用参考档的时间记录，与 --file 的效果一样。
d 设定时间与日期，可以使用各种不同的格式。
t 设定档案的时间记录，格式与 date 指令相同。
--no-create 不会建立新档案。
--help 列出指令格式。
--version 列出版本讯息。

范例：

最简单的使用方式，将档案的时候记录改为现在的时间。若档案不存在，系统会建立一个新的档案。

touch file
touch file1 file2

将 file 的时间记录改为 5 月 6 日 18 点 3 分，公元两千年。时间的格式可以参考 date 指令，至少需输入 MMDDHHmm ，就是月日时与分。

touch -c -t 05061803 file
touch -c -t 050618032000 file

将 file 的时间记录改变成与 referencefile 一样。

touch -r referencefile file

将 file 的时间记录改成 5 月 6 日 18 点 3 分，公元两千年。时间可以使用 am, pm 或是 24 小时的格式，日期可以使用其他格式如 6 May 2000 。

touch -d "6:03pm" file
touch -d "05/06/2000" file
touch -d "6:03pm 05/06/2000" file

touch 也可以制造一个空档(0 byte).例如DHCP Server所需的/etc/dhcpd.leases,dhcpd 必须要有这个档案才能运作正常.[root@/root]#touch /etc/dhcpd.leases[root@/root]#ls -l /etc/dhcpd.leases-rw-r--r-- 1 root root 0 Jul 3 05:50 /etc/dhcpd.leases

记得上一次重灌前把/etc下的设定档tar起来，重灌好之后把原有设定还原，却发现系统检查设定档的时间有问题，这个时候用
find /etc -name * -exec touch {};

就可以把设定档的时间更新到与现在一致了。

Taiwan's IC Industry: Review of Q1 and Outlook for 2007

2007-11-06T20:16:00.000+08:00

Taiwan's IC Industry: Review of Q1 and Outlook for 2007

ITRI IEK-ITIS Project

1. 2007 Q1 Industry Overview

According to statistics released by the Industrial Economics and Knowledge Center (IEK) of the Industrial Technology Research Institute (ITRI), the production value of Taiwan's IC industry (including design, manufacturing, packaging and testing) was NT$339.5 billion in the first quarter of 2007. This represented a drop of 11.4% over the previous quarter (Q4 2006), but an increase of 10.6% relative to the first quarter of 2006 (the same period of the previous year). The design sector accounted for NT$84 billion (down 9.3% from Q4 2006, up 15.4% from Q1 2006), manufacturing for NT$182.5 billion (down 14.6% from Q4 2006, up 11.6% from Q1 2006), packaging for NT$50 billion (down 6.5% from Q4 2006, up 2.0% from Q1 2006), and testing for NT$23 billion (down 2.1% from Q4 2006, up 6.0% from Q1 2006). The following is a survey of the performance of Taiwan's IC design, manufacturing, packaging, and testing industries during the first quarter of 2007.

A. IC Design

In LCD-related IC design, revenue growth slowed due to the influence of flat screen product shipments during the first quarter; shipments of optical storage chipsets and DVD player chips remained steady. Shipments of low-grade mobile phones from China and India increased steadily, boosting mobile phone IC manufacturers' revenue. In the area of information product chipsets, Intel's and AMD's increasing focus on the embedded market, as well as NVIDIA's and ATI's reliance on their dominating graphics technology to lock up market share, has constricted the market for Taiwan's PC chipsets. In summary, the IC design sector had a production value of NT$84 billion during the first quarter of 2007; this figure was down 9.3% from the fourth quarter of 2006, but up 15.4% from the first quarter of 2006.

B. IC Manufacturing

Among Taiwan's two leading IC foundries, TSMC had revenue of NT$63.3 billion during the first quarter of 2007--a drop of 14% relative to the previous quarter--while UMC had revenue of NT$23 billion--which was similarly down by 12% over the previous quarter. These drops can mainly be attributed to customers' inventory adjustments. Spot prices of mainstream 512Mb DDR2 DRAM quickly fell from US$5 to below US$3 during the first quarter, and are now very close to manufacturers' production cost, which has also affected revenue performance. IC manufacturers had a production value of NT$182.5 billion during the first quarter of 2007; this represented a drop of 14.6% from the fourth quarter of 2006, but growth of 11.6 from the first quarter of that year.

C. IC Packaging and Testing

Seasonal factors and unfavorable market conditions caused the packaging and testing industry fall into a slump during the first quarter. Continued demand for packaging and testing of LCD driver ICs, memory cards, computer chipsets, chips for 3G mobile phones, and other communications and graphics chips will drive grow in the future, however. In summary, the IC packaging industry had production value of NT$50 billion during the first quarter of 2007, down 6.5% from the final quarter of 2006, but up 2.0% from the first quarter of that year. The testing industry had production value of NT$23 billion during the first quarter, which was down by 2.1% from the fourth quarter, but up 6.0% from the first quarter of 2006.

2. Outlook for the Second Quarter and all of 2007

In the design sector, demand will be driven by systems companies' continued introduction of popular new products like the Nintendo Wii, the Sony PS3 and the Apple iPhone. Taiwan's IC design industry is also expected to benefit from the ongoing effects of Microsoft's Vista, demand sparked by falling digital TV prices, and other business opportunities created by popular products. The IC industry is projected to have a production value of NT$87 billion during the second quarter, and achieve 3.6% growth relative to the first quarter. Production value for all of 2007 is projected to be NT$361.5 billion, which represents growth of 11.8% over 2006.

In the manufacturing sector, continued inventory adjustments by foundry customers will lead to a steadily increasing proportion of 90nm and 65nm advanced process product shipments. It is expected that Taiwan's IC foundries will have a second-quarter production value of NT$102.9 billion, a rise of 12.6% from the first quarter. The price of DRAM has fallen steadily, and is seen as bottoming out during Q2. This will drag down manufacturers' revenues and profits. The IC manufacturing industry as a whole is projected to have a production value of NT$172.9 billion during the second quarter, a 5.3% drop relative to Q1. The industry's production value for all of 2007 is projected to be NT$833.4 billion, growing 8.7% from 2006.

In the packaging and testing sector, demand for packaging and testing of chips used in PCs, mobile phones and digital consumer electronics products and peripherals may grow. Microsoft's Vista is expected to sustain growth in PC-related markets. The 2008 Beijing Olympics should also provide opportunities for the consumer electronics industry. Demand for mid-range and low end products in India and other emerging markets will continue. The production value of the packaging and testing industry is expected to reach NT$76.5 billion in the second quarter of 2007, an increase of 4.8% over the first quarter. Production value for all of 2007 is projected to be NT$341.3 billion, an increase of 12.6% relative to 2006.

Synopsys synthesis tutorial

2007-11-06T20:14:00.001+08:00

some tutorials from the synopsys install directoy,maybe it's too old for the latest tool.

点击下载, Click for Download

keywords:Design compiler ,Power Compiler,Scan chain insertion,script,synthesis example,DC脚本,综合实例

EFA Flex License Generator 0.4beta

2007-11-06T20:13:00.002+08:00

A very power Flex License Generator: (点击下载)(Click to Download)
Related link:
http://www.woodmann.net/crackz/Flexlm.htm

License For The vendor list below:
Actel
AgilentADS_1.5
Aldec Active HDL
Aldec Active HDL70
Aldec RIVIERA
Allegro14_Cdslmd
Allegro14_PSLD
Altera
AnalyticalGraphics_STK42
AnsoftMaxWell
AnsoftSerenade_8.5
Aplac76
Asset
Atlass
Avanti
AvantiCorp
Cadence Design Systems
Cadence Design Systems_6
Cadence Design Systems_7
Cadence Design Systems_71
Cadence
CadencePSD_14.2
Concept_GateVision
CST_MicroWave_Studio_3.2
Dolphin-Smash
FPGACompilerII_3.6
GerbTool_10
HyperLynx_6.0
Laker LayoutEditor
Laker
Laker1
Laker_Any
LSI-Logic
Magma
Mars_Synplify
Micromagic
modeltech
ModelTech71
ModeltechBundle
MWO2001
NovasDebussy_5
NovasLaker
novas_50v16
Simplex
SonetLite
SynaptiCad_7.5
Synopsys
Synplicity
Synplicity_6.2
Synplify Synplicity
TransEDA
TranslogicHDLEntry_5
verisity
Veritools
Verplex
Viewlogic
VirageLogic
X-Tek

关于状态机写法的一点看法 FSM Finite State Machine

2007-11-06T20:13:00.001+08:00

关于以下两种状态机，说点自己的见解。
1. reg control_signal;
always @(c_s or other_sensitive_variable)
begin
control_signal = 1'b0;
......
case(c_s)
state0:
state1:
begin
control_signal = 1'b1;
if(sensitive_variable1)
n_s = state2;
end
...
endcase
end
always @(clk or rstj)
if(!rstj)
c_s <= case_init ;
else
c_s <= n_s;
2. wire control_signal = c_s == state2;

always @(c_s or other_sensitive_variable)

begin

case(c_s)

state0:

state1:

if(sensitive_variable1)

n_s = state2;

...

endcase

end

always @(clk or rstj)

if(!rstj)

c_s <= state_init ;

else

c_s <= n_s;

control_signal调用：

always @(posedge clk or negedge rstj)

if(!negedge rstj)

reg_a <= 1'b0;

else if(control_signal)

reg_a <= reg_x;

reg_x会在state1的时候就ready，当sensitive_variable1有效时，reg_x已经ready。

观察两种写法control_signal的情况：

1.当state1向state2切换时，reg_x的值同时被赋给reg_a;

2.当state1向state2切换时，control_signal被赋1，但此时reg_x的值需要等待1T之后才能赋给reg_a.

分析：

1.两种写法都是可以的，只需要保持数据和控制一致；

2.第二种写法的可读性和维护性更好；

3.初步看来，如果数据控制不做特别的处理的话，第一种写法在每种状态的切换可以省下一个T，对于时间要求很紧促，或者状态切换较多的情况下采用第一种较好。

以上只是对项目中看到的两种状态机的写法的一些个人见解，如有不妥之处，请Email给我指出，Thanks! ^_^

Analog Design 100 tips[转]

2007-11-06T20:12:00.000+08:00

From edaboard:

=============================================

1/ Capacitors and resistors have parasitic inductance, about 0.4nH for surface mount and 4nH for a leaded component.

2/ If you don"t want a high bandwidth transistor to oscillate place lossy components in at least 2 of the 3 leads. Ferrite beads work well.

3/ When taking DC measurements in a circuit and they don"t make sense, suspect that something is oscillating.

4/ Opamps will often oscillate when driving capacitive loads.

5/ The base-emitter voltage Vbe of a small signal transistor is about 0.65v and drops about 2mV/deg C. Vbe goes down with increasing temp.

6/ Multiply 0.13nV by the square root of the ohmic value of a resistor to find the noise in a 1Hz bandwidth. Then multiply by the square root of the BW in Hz gives the total noise voltage.

7/ Johnson noise current goes down with a increase in resistance.

8/ The impedance looking into the emitter of a transistor at room temp is 26Ohm/Ie in mA

9/ All amplifiers are differential in that they are referenced to ground somewhere.

10/ Typical metal film resistor has a temp coef of about 100 ppm/deg C

11/ The input noise voltage of a quiet op amp is 1nv/sqrt(Hz) but there are plenty available with 20nV/sqrt(Hz). Op amps with bipolar front-ends have lower voltage noise and higher current noise than those with FET front-ends

12/ Using an LC circuit as a power supply filter can actually multiply the power supply noise at the filter"s resonant frequency. Use inductor with low Q to overcome this.

13/ Use comparators for comparing and op amps for amplifying and don"t even think of mixing the two.

14/ Ceramic caps with any other dielectric other than NPO should only be used for bypass applications.

15/ An N-channel enhancement-mode FET needs +ve voltage on the gate-source to conduct form drain-source.

16/ Small signal JFETS work very well as low-leakage diodes by connecting drain & source together in log current-to-voltage converters and low leakage input protection. Small signal bipolars with b-c tied together will also make nice low-leakage diodes.

17/ With low pass filter use Bessel for least amount of overshoot in the time domain, and Cauer (or elliptic) for fastest rolloff in the freq domain.

18/ dB is always 10 times the log of the ratio of 2 powers.

19/ At low frequencies, the current in the collector of a transistor is in phase with the applied current at the base. At high frequencies the current at the collector lags by 90deg. You must appreciate this simple fact to understand high frequency oscillators.

20/ The most common glass-epoxy PCB material (FR4) has a dielectric constant of about 4.3 To make a trace with a characteristic impedance of 100 Ohm, use a trace thickness of about 0.4 times the thickness of the board with a ground plane on the opposite side. For a 50Ohm trace make it 2 times the thickness.

21/ If you need a programmable dynamic current source, find out about operational transconductance amps. Most of the problem is figuring out when you need a programmable dynamic current source.

22/ A CMOS output with an emitter follower can drive a 5V relay nicely as the relays normally have a must-make spec of 3.5V. This saves power and require no flyback components.

23/ Typical thermocouple potential is 30uV/degC. Route signals differentially, along the same path, avoid temp gradients. DPDT latching relays won"t heat up when multiplexing these signals.

24/ You SHOULD be bothered by a design that looks messy, cluttered or indirect. This uncomfortable feeling is one of the few indications that there"s a better way.

25/ Avoid drawing any current from the wiper of a potentiometer. The resistance of the wiper contact will cause problems (local heating, noise offsets etc.)

26/ Most digital phase detectors have a deadband where the analog output does not change over the small range where the 2 inputs are coincident. This often-ignored fact has helped to create some very noisy PLL"s (Use a high val bleeding resistor to always ensure current flow in the deadband)

27/ The phase noise of a phase-locked VCO will be at least 6dB worse than the phase noise of the divided reference for each octave between the comparison frequency and the VCO output frequency. Avoid low-comparison frequencies.

28/ You can almost always determine the leads of a bipolar transistor with an ohm meter. b-e and b-c junctions will measure like a diode with the b-c junction reading slightly lower than the b-e junction when forward biased.

29/ For low distortion, the drains (or collectors) of a differential amp"s front-end should be bootstrapped to the source (or emitter) so that the voltages on the part are not modulated by the input signal.

30/ If your design uses a $3 op amp, and you will be making a thousand of them, you have just spend $3000. Are you smart enough to figure out how to use a $.30 op amp instead?

31/ The Q of an LC tank circuit is dominated by the losses in the inductor in terms of series R. Q=omega.L/R

32/ Leakage current doubles for every 10degC increase in temp.

33/ When inputs to most JFET op amps exceed the common-mode range for the part, the output may reverse polarity. This artifact will haunt the designers of these parts for the rest of their lives, as it should!

34/ Understand the difference between "make-before-break" and "break-before-make" when you specify switches.

35/ 3 Terminal voltage regulators in the TO-220 packages are wonderful parts. They are cheap, rugged, thermally protected and very versatile. Use them virtually any place where you need a protected power transistor. They also make nice AM power-modulators.

36/ Use step recovery diode where you need fast edges under 100pS (hot-carrier is even faster)

37/ The old 723 regulator is still one of the lowest noise regulators around! (2.5uVrms 100Hz-10k)

38/ You can make a very simple oscillator with one diac, cap and a resistor.

39/ NPN transistors are normally superior to their PNP counterpart in performance.

40/ Typical spec in some databooks should read "Seen it once". Always work with the worst spec of the part when doing a design.

41/ Don"t just copy circuits from application notes without understanding completely how it operates, and the reason for the choice of values.

42/ Dealing with crystals, make sure you understand the difference between series and parallel resonant. In a circuit, crystal frequency can generally be slightly lowered by placing a inductor in series and increased by a capacitor in series.

43/ Power MOSFETS on-resistance will have a -ve temp coef and not +ve at low current levels. This is important to remember when paralleling devices.

44/ Lowest noise figure of a RF transistor is not normally where the input is perfectly matched.

45/ Many un-stable RF devices can be made stable by loading the input or the output by a simple resistor, either in series or parallel.

46/ You trade gain for bandwidth.

47/ Push-pull power invertors using bipolars are risky and can saturate the core because of hysteresis stepping (use power fets)

48/ The Al value of a core will increase up to 50% or more under current transients.

49/ Be aware of leakage inductance when switching. V=L(dI/dt)

50/ The harder you turn-on a power transistor, the longer it will take to turn off.( the part where you burn the joules in the device)

51/ Always remember the Miller guy.

52/ In fault-finding a circuit, don"t overlook the obvious. (is there power?)

53/ What is a ground loop, and how to avoid it.

54/ 120 is a better number than 240 when using LM3XX type adjustable regulators.

55/ The lower comparator in the old 555 may have quite a long storage time.

56/ ZERO-ESR caps may do more harm than good.

57/ A correctly configured audio power amplifier will give more distortion in Class-AB, not less, because of the abrupt gain changes inherent in switching from A to B every cycle.

58/ Be a STAR when it comes to ground matters.

59/ Know when you need to use a Zobel network.

60/ Use current mirrors and mirror your current.

61/ Heatsink eff decreases with height above sealevel.

62/ A matt-black heatsink is much better than a shiny one.

63/ Ignoring secondary breakdown can be costly.

64/ Understand fuses and fuse ratings, fast and slow. Do you know when to use a semiconductor-fuse?

65/ Charge balancing resistors are a must when stacking serie-parallel high voltage capacitor banks.

66/ You must understand DC-restoration otherwise you will have a hard time designing Z-modulation in CRT circuits.

67/ Display 6 vert div low freq on a scope, increase the freq (make sure the source is constant amplitude) until display drops to 4.2 div. That is the true 3dB BW of the scope. (scope-source impedance should be matched)

68/ Doing a measurement with your DMM in the ACV position on your DC circuit will give a quick indication of any excess ripple on the supply when you don"t have a scope at hand.

69/ Dly timebase on a scope is very useful once you figured out when, why and how to use it.

70/ Know what to expect before you measure, otherwise any measurement is meaningless.

71/ Op amps. Output will swing in the direction that will force the inv-input level to try come closer to the non-inv input level.

72/ Understand virtual ground, slew-rate, CMRR and PSRR. (CMRR decrease with increase in freq)

73/ Making measurements near a spec-analalyzer"s noise floor will give 3dB errors.

74/ Understand the phase-noise limitations of the analyzer when making such measurements on oscillators.

75/ In a LC oscillator add some C with -ve temp coef to cancel the +ve temp coef of the L for min drift with temp.

76/ Less drift will result from making C with a few parallel caps, to reduce the heating effect of the oscillating current when spread out over a larger plate area.

77/ You will get more tuning range with the same LC combination in a Clapp than in a Colpitts circuit.

78/ High-Q tuned LC filters will have more insertion loss.

79/ Williams"s Rule (Guru at Linear Tech) for precision op amp circuits: " Always invert (except when you can"t)"

80/ Cuk is not a kind of locomotive.

81/ If you don"t know how to make a design better, find out what makes it worse.

82/ Sometimes you know just enough to be dangerous.

83/ Impedance will reflect back as the square of the turns ratio.

84/ If you could design a component with the characteristics of a finger it could cure many design problems and you will be rich.

85/ Get nervous when the customer you are trying to help doesn"t even have a scope.

86/ Specs quoted by reps always exceed those by Engineering.

87/ A bad (Engineer) workman always blames his tools.

88/ Don"t believe everything that a SPICE program spits out.

89/ It is easy to get the color code of a 1kOhm and 12Ohm resistor mixed up when you are in a hurry.

90/ I bet one could write a thesis about the ability of probes to get tangled-up on a bench.

91/ DMM can upset sensitive circuits from noise generated inside it.

92/ When probing directly on a crystal of a uP, use 10kOhm or so resistor in series with the probe tip to prevent loading from stopping the osc.

93/ It is easier to see what is happening on the ports using a scope when you trigger one chan against the cpu clock.

94/ National once made a bad op amp many years ago that some Engineers referred to it as "Jelly Beans"

95/ The moment you can start to notice distortion on an oscilloscope it is already way past being acceptable.

96/ Be big enough to say "I don"t know", people will respect you more.

97/ The best designer is often working in the marketing department.

98/ Some remarkable discoveries/inventions were made by people that knew very little about the subject. Don"t fall into a groove in you thinking process.

99/ The Peter-Principle : Everybody will be promoted up to his own level of incompetence. http://pespmc1.vub.ac.be/PETERPR.html

100/ END-Enjoy

Linux Test Command usage

2007-11-06T20:11:00.002+08:00

test 文件运算符

利用这些运算符，您可以在程序中根据对文件类型的评估结果执行不同的操作：

-b file 如果文件为一个块特殊文件，则为真
-c file 如果文件为一个字符特殊文件，则为真
-d file 如果文件为一个目录，则为真
-e file 如果文件存在，则为真
-f file 如果文件为一个普通文件，则为真
-g file 如果设置了文件的 SGID 位，则为真
-G file 如果文件存在且归该组所有，则为真
-k file 如果设置了文件的粘着位，则为真
-O file 如果文件存在并且归该用户所有，则为真
-p file 如果文件为一个命名管道，则为真
-r file 如果文件可读，则为真
-s file 如果文件的长度不为零，则为真
-S file 如果文件为一个套接字特殊文件，则为真
-t fd 如果 fd 是一个与终端相连的打开的文件描述符（fd 默认为 1），则为真
-u file 如果设置了文件的 SUID 位，则为真
-w file 如果文件可写，则为真
-x file 如果文件可执行，则为真

shell变量的用法[tips]

2007-11-06T20:11:00.001+08:00

if ($?Variable) then
变量名前加个"？"，判断该变量是否存在，不care变量的值，定义了即为真。

sed命令详解!![转]

2007-11-06T20:10:00.001+08:00

Table of Contents
1. Sed简介
2. 定址
3. Sed命令
4. 选项
5. 元字符集
6. 实例
7. 脚本

1. Sed简介

sed是一种在线编辑器，它一次处理一行内容。处理时，把当前处理的行存储在临时缓冲区中，称为"模式空间"（pattern space），接着用sed命令处理缓冲区中的内容，处理完成后，把缓冲区的内容送往屏幕。接着处理下一行，这样不断重复，直到文件末尾。文件内容并没有改变，除非你使用重定向存储输出。Sed主要用来自动编辑一个或多个文件；简化对文件的反复操作；编写转换程序等。以下介绍的是Gnu版本的Sed 3.02。

2. 定址

可以通过定址来定位你所希望编辑的行，该地址用数字构成，用逗号分隔的两个行数表示以这两行为起止的行的范围（包括行数表示的那两行）。如1，3表示1，2，3行，美元符号($)表示最后一行。范围可以通过数据，正则表达式或者二者结合的方式确定。

3. Sed命令

调用sed命令有两种形式：

sed [options] 'command' file(s)

sed [options] -f scriptfile file(s)

<
a\
在当前行后面加入一行文本。

b lable
分支到脚本中带有标记的地方，如果分支不存在则分支到脚本的末尾。

c\
用新的文本改变本行的文本。

d
从模板块（Pattern space）位置删除行。

D
删除模板块的第一行。

i\
在当前行上面插入文本。

h
拷贝模板块的内容到内存中的缓冲区。

H
追加模板块的内容到内存中的缓冲区

g
获得内存缓冲区的内容，并替代当前模板块中的文本。

G
获得内存缓冲区的内容，并追加到当前模板块文本的后面。

l
列表不能打印字符的清单。

n
读取下一个输入行，用下一个命令处理新的行而不是用第一个命令。

N
追加下一个输入行到模板块后面并在二者间嵌入一个新行，改变当前行号码。

p
打印模板块的行。

P（大写）
打印模板块的第一行。

q
退出Sed。

r file
从file中读行。

t label
if分支，从最后一行开始，条件一旦满足或者T，t命令，将导致分支到带有标号的命令处，或者到脚本的末尾。

T label
错误分支，从最后一行开始，一旦发生错误或者T，t命令，将导致分支到带有标号的命令处，或者到脚本的末尾。

w file
写并追加模板块到file末尾。

W file
写并追加模板块的第一行到file末尾。

!
表示后面的命令对所有没有被选定的行发生作用。

s/re/string
用string替换正则表达式re。

=
打印当前行号码。

#
把注释扩展到下一个换行符以前。

以下的是替换标记

g表示行内全面替换。

p表示打印行。

w表示把行写入一个文件。

x表示互换模板块中的文本和缓冲区中的文本。

y表示把一个字符翻译为另外的字符（但是不用于正则表达式）

4. 选项
<
-e command, --expression=command
允许多台编辑。

-h, --help
打印帮助，并显示bug列表的地址。

-n, --quiet, --silent
取消默认输出。

-f, --filer=script-file
引导sed脚本文件名。

-V, --version
打印版本和版权信息。

5. 元字符集
<
^
锚定行的开始如：/^sed/匹配所有以sed开头的行。

$
锚定行的结束如：/sed$/匹配所有以sed结尾的行。

.
匹配一个非换行符的字符如：/s.d/匹配s后接一个任意字符，然后是d。

*
匹配零或多个字符如：/*sed/匹配所有模板是一个或多个空格后紧跟sed的行。

[]
匹配一个指定范围内的字符，如/[Ss]ed/匹配sed和Sed。

[^]
匹配一个不在指定范围内的字符，如：/[^A-RT-Z]ed/匹配不包含A-R和T-Z的一个字母开头，紧跟ed的行。

$..$
保存匹配的字符，如s/$love$able/\1rs，loveable被替换成lovers。

&
保存搜索字符用来替换其他字符，如s/love/**&**/，love这成**love**。

\<
锚定单词的开始，如:/\

\>
锚定单词的结束，如/love\>/匹配包含以love结尾的单词的行。

x\{m\}
重复字符x，m次，如：/0\{5\}/匹配包含5个o的行。

x\{m,\}
重复字符x,至少m次，如：/o\{5,\}/匹配至少有5个o的行。

x\{m,n\}
重复字符x，至少m次，不多于n次，如：/o\{5,10\}/匹配5--10个o的行。

6. 实例
删除：d命令
$ sed '2d' example-----删除example文件的第二行。

$ sed '2,$d' example-----删除example文件的第二行到末尾所有行。

$ sed '$d' example-----删除example文件的最后一行。

$ sed '/test/'d example-----删除example文件所有包含test的行。

替换：s命令
$ sed 's/test/mytest/g' example-----在整行范围内把test替换为mytest。如果没有g标记，则只有每行第一个匹配的test被替换成mytest。

$ sed -n 's/^test/mytest/p' example-----(-n)选项和p标志一起使用表示只打印那些发生替换的行。也就是说，如果某一行开头的test被替换成mytest，就打印它。

$ sed 's/^192.168.0.1/&localhost/' example-----&符号表示替换换字符串中被找到的部份。所有以192.168.0.1开头的行都会被替换成它自已加 localhost，变成192.168.0.1localhost。

$ sed -n 's/$love$able/\1rs/p' example-----love被标记为1，所有loveable会被替换成lovers，而且替换的行会被打印出来。

$ sed 's#10#100#g' example-----不论什么字符，紧跟着s命令的都被认为是新的分隔符，所以，"#"在这里是分隔符，代替了默认的"/"分隔符。表示把所有10替换成100。

选定行的范围：逗号
$ sed -n '/test/,/check/p' example-----所有在模板test和check所确定的范围内的行都被打印。

$ sed -n '5,/^test/p' example-----打印从第五行开始到第一个包含以test开始的行之间的所有行。

$ sed '/test/,/check/s/$/sed test/' example-----对于模板test和west之间的行，每行的末尾用字符串sed test替换。

多点编辑：e命令
$ sed -e '1,5d' -e 's/test/check/' example-----(-e)选项允许在同一行里执行多条命令。如例子所示，第一条命令删除1至5行，第二条命令用check替换test。命令的执行顺序对结果有影响。如果两个命令都是替换命令，那么第一个替换命令将影响第二个替换命令的结果。

$ sed --expression='s/test/check/' --expression='/love/d' example-----一个比-e更好的命令是--expression。它能给sed表达式赋值。

从文件读入：r命令
$ sed '/test/r file' example-----file里的内容被读进来，显示在与test匹配的行后面，如果匹配多行，则file的内容将显示在所有匹配行的下面。

写入文件：w命令
$ sed -n '/test/w file' example-----在example中所有包含test的行都被写入file里。

追加命令：a命令
$ sed '/^test/a\\--->this is a example' example<-----'this is a example'被追加到以test开头的行后面，sed要求命令a后面有一个反斜杠。

插入：i命令
$ sed '/test/i\\

new line

-------------------------' example

如果test被匹配，则把反斜杠后面的文本插入到匹配行的前面。

下一个：n命令
$ sed '/test/{ n; s/aa/bb/; }' example-----如果test被匹配，则移动到匹配行的下一行，替换这一行的aa，变为bb，并打印该行，然后继续。

变形：y命令
$ sed '1,10y/abcde/ABCDE/' example-----把1--10行内所有abcde转变为大写，注意，正则表达式元字符不能使用这个命令。

退出：q命令
$ sed '10q' example-----打印完第10行后，退出sed。

保持和获取：h命令和G命令
$ sed -e '/test/h' -e '$G example-----在sed处理文件的时候，每一行都被保存在一个叫模式空间的临时缓冲区中，除非行被删除或者输出被取消，否则所有被处理的行都将打印在屏幕上。接着模式空间被清空，并存入新的一行等待处理。在这个例子里，匹配test的行被找到后，将存入模式空间，h命令将其复制并存入一个称为保持缓存区的特殊缓冲区内。第二条语句的意思是，当到达最后一行后，G命令取出保持缓冲区的行，然后把它放回模式空间中，且追加到现在已经存在于模式空间中的行的末尾。在这个例子中就是追加到最后一行。简单来说，任何包含test的行都被复制并追加到该文件的末尾。

保持和互换：h命令和x命令
$ sed -e '/test/h' -e '/check/x' example -----互换模式空间和保持缓冲区的内容。也就是把包含test与check的行互换。

7. 脚本
Sed脚本是一个sed的命令清单，启动Sed时以-f选项引导脚本文件名。Sed对于脚本中输入的命令非常挑剔，在命令的末尾不能有任何空白或文本，如果在一行中有多个命令，要用分号分隔。以#开头的行为注释行，且不能跨行。

比如，如果要打印出含有字串"1024"的行，我就可能会用：
cat filename sed �Cn '/1024/p'

Important Themes in Digital Design[转]

2007-11-06T20:08:00.000+08:00

Important Themes in Digital Design

Good tools do not guarantee good design, but they help a lot by taking the pain out of doing things right.
Digital circuits have analog characteristics.
Know when to worry and when not to worry about the analog aspects of digital design.
Always document your designs to make them understandable by yourself and others.
Associate active levels with signal names and practice bubble-to-bubble logic design.
Understand and use standard functional building blocks.
Design for minimum cost at the system level, including your own engineering effort as part of the cost.
State-machine design is like programming; approach it that way.
Use programmable logic to simplify designs, reduce cost, and accommodate lastminute modifications.
Avoid asynchronous design. Practice synchronous design until a better methodology comes along.
Pinpoint the unavoidable asynchronous interfaces between different subsystems and the outside world, and provide reliable synchronizers.
Catching a glitch in time saves nine.

ECO

2007-11-06T20:07:00.000+08:00

前提：综合时要keep hierarchy, 确保逻辑不被打散，做ECO时能快速定位到需要修改的地方。步骤：
1. 修改rtl code，做rtl level 的simulation，确保修改思想是正确的
2. 查找netlist，定位到需要修改地方，理清周边逻辑，尤其是对于有clock gating的情况
3. 少量逻辑的增加可手动例化一些库单元，或写个module综合一下
4. 确保修改后逻辑和时序与预期的一致
5. Formal Check，可用LEC，比对netlist和rtl code的一致性，确保你netlist修改正确
6. gate level simulation
7. To backend

TSMC 0.25um spec-standard cell

2007-11-06T20:05:00.002+08:00

下面为spec，如果需要db文件，请与我Email联系。
tsmc25.pdf 点击下载

ASIC设计原则之我见

2007-11-06T20:05:00.001+08:00

1. 功能实现是基本的，但光实现功能是基本不行的；
2. 存储单元比逻辑运算单元更占面积，所以与其花很多时间在运算单元的精简上，不如在存储单元的安排上多花点功夫；
3. 凡事须从整体出发，但细节也不能忽视，在两者矛盾的地方细节应服从整体；
4. 绝对的平衡是做不到的，但只有力求平衡才能最大限度把design做到更优；
5. 设计必须留一定的裕量，但裕量不宜过大，在灵活性、可继承性和面积、Timing之间需求最佳平衡；
6. 好的架构对应着小的面积和好的Timing；
7. 设计和验证同步进行，考虑设计的同时应该考虑验证；
8. Co-Work,Schedule和Archtecture同样重要。

[转帖]Tip - 同时更改所有IO管脚的电平标准

2007-11-06T20:04:00.001+08:00

转自：http://www.rickysu.com/bo/read.php/83.htm
要更改所有IO Pin的IO Standard，可以打开PACE，选择所有管脚（通过shift或ctrl键多选），按右键，Create Constraints，然后自己选需要的吧：）

ISE8.2 sn 序列号 serial number ID

2007-11-06T20:03:00.000+08:00

ISE 8.2: 5876-1279-7287-2760

采用批处理文件进行文件处理

2007-11-06T20:02:00.001+08:00

@echo offset cnt=0:loopset /a cnt=%cnt%+1copy /y .\Book.gif .\%cnt%.\if not %c%==101 goto looppause
1. 对变量进行运算操作：set /a
2. 路径中包含变量的写法： .\%cnt%.\

***********点点滴滴积累*****************

数字集成电路设计后端流程[转贴]

2007-11-06T19:10:00.000+08:00

转自：http://www.edacn.net/bbs/viewthread.php?tid=25227&fpage=1&highlight
1. 数据准备。对于 CDN 的 Silicon Ensemble而言后端设计所需的数据主要有是Foundry厂提供的标准单元、宏单元和I/O Pad的库文件，它包括物理库、时序库及网表库，分别以.lef、.tlf和.v的形式给出。前端的芯片设计经过综合后生成的门级网表，具有时序约束和时钟定义的脚本文件和由此产生的.gcf约束文件以及定义电源Pad的DEF（Design Exchange Format）文件。(对synopsys 的Astro 而言，经过综合后生成的门级网表，时序约束文件 SDC 是一样的,Pad的定义文件--tdf ， .tf 文件 --technology file， Foundry厂提供的标准单元、宏单元和I/O Pad的库文件就与FRAM, CELL view, LM view 形式给出(Milkway 参考库 and DB, LIB file)
2. 布局规划。主要是标准单元、I/O Pad和宏单元的布局。I/O Pad预先给出了位置，而宏单元则根据时序要求进行摆放，标准单元则是给出了一定的区域由工具自动摆放。布局规划后，芯片的大小，Core的面积，Row的形式、电源及地线的Ring和Strip都确定下来了。如果必要在自动放置标准单元和宏单元之后，你可以先做一次PNA(power network analysis）--IR drop and EM .
3. Placement -自动放置标准单元。布局规划后，宏单元、I/O Pad的位置和放置标准单元的区域都已确定，这些信息SE（Silicon Ensemble）会通过DEF文件传递给PC(Physical Compiler),PC根据由综合给出的.DB文件获得网表和时序约束信息进行自动放置标准单元，同时进行时序检查和单元放置优化。如果你用的是PC +Astro那你可用write_milkway, read_milkway 传递数据。
4. 时钟树生成(CTS Clock tree synthesis) 。芯片中的时钟网络要驱动电路中所有的时序单元，所以时钟源端门单元带载很多，其负载延时很大并且不平衡，需要插入缓冲器减小负载和平衡延时。时钟网络及其上的缓冲器构成了时钟树。一般要反复几次才可以做出一个比较理想的时钟树。---Clock skew.
5. STA 静态时序分析和后仿真。时钟树插入后，每个单元的位置都确定下来了，工具可以提出Global Route形式的连线寄生参数，此时对延时参数的提取就比较准确了。 SE把.V和.SDF文件传递给PrimeTime做静态时序分析。确认没有时序违规后，将这来两个文件传递给前端人员做后仿真。对Astro 而言，在detail routing 之后，用starRC XT 参数提取，生成的E.V和.SDF文件传递给PrimeTime做静态时序分析，那将会更准确。
6. ECO(Engineering Change Order)。针对静态时序分析和后仿真中出现的问题，对电路和单元布局进行小范围的改动.
7. Filler的插入(pad fliier, cell filler)。Filler指的是标准单元库和I/O Pad库中定义的与逻辑无关的填充物，用来填充标准单元和标准单元之间，I/O Pad和I/O Pad之间的间隙，它主要是把扩散层连接起来，满足DRC规则和设计需要。
8. 布线(Routing)。Global route-- Track assign --Detail routing--Routing optimization 布线是指在满足工艺规则和布线层数限制、线宽、线间距限制和各线网可靠绝缘的电性能约束的条件下，根据电路的连接关系将各单元和I/O Pad用互连线连接起来，这些是在时序驱动(Timing driven ) 的条件下进行的，保证关键时序路径上的连线长度能够最小。--Timing report clear
9. Dummy Metal的增加。Foundry厂都有对金属密度的规定，使其金属密度不要低于一定的值，以防在芯片制造过程中的刻蚀阶段对连线的金属层过度刻蚀从而降低电路的性能。加入Dummy Metal是为了增加金属的密度。
10. DRC和LVS。DRC是对芯片版图中的各层物理图形进行设计规则检查(spacing ,width)，它也包括天线效应的检查，以确保芯片正常流片。LVS主要是将版图和电路网表进行比较，来保证流片出来的版图电路和实际需要的电路一致。DRC和LVS的检查--EDA工具 Synopsy hercules/ mentor calibre/ CDN Dracula进行的.Astro also include LVS/DRC check commands.
11. Tape out。在所有检查和验证都正确无误的情况下把最后的版图GDSⅡ文件传递给Foundry厂进行掩膜制造。

常用IC习语缩写

2007-11-06T19:09:00.000+08:00

DUT Design Under Test
BIST Build In Self Test
SOP Standard of Process
TB Test Bench
RTL Register Transfer Level
LEC Logic Equivalence Checking
ENV Envirament
ECO Engineer Change Order
PCI Periphral Component Interconnect
STA Static Timing Analysis
ASIC Application Specific Integerated Circuit
DFT Desing For Testability
SRV Simulation Result Verification
TSTL Toshiba Stardard Tester Interface
ATE Automatic Test Equipment

Xilinx FPGA全局时钟和第二全局时钟资源的使用方法[转贴]

2007-11-06T19:08:00.001+08:00

目前，大型设计一般推荐使用同步时序电路。同步时序电路基于时钟触发沿设计，对时钟的周期、占空比、延时和抖动提出了更高的要求。为了满足同步时序设计的要求，一般在FPGA设计中采用全局时钟资源驱动设计的主时钟，以达到最低的时钟抖动和延迟。 FPGA全局时钟资源一般使用全铜层工艺实现，并设计了专用时钟缓冲与驱动结构，从而使全局时钟到达芯片内部的所有可配置单元(CLB)、I/O单元(IOB)和选择性块RAM(Block Select RAM)的时延和抖动都为最小。为了适应复杂设计的需要，Xilinx的FPGA中集成的专用时钟资源与数字延迟锁相环(DLL)的数目不断增加，最新的Virtex II器件最多可以提供16个全局时钟输入端口和8个数字时钟管理模块(DCM)。与全局时钟资源相关的原语常用的与全局时钟资源相关的Xilinx器件原语包括：IBUFG、IBUFGDS、BUFG、BUFGP、BUFGCE、BUFGMUX、BUFGDLL和DCM等，如图1所示。
1. IBUFG即输入全局缓冲，是与专用全局时钟输入管脚相连接的首级全局缓冲。所有从全局时钟管脚输入的信号必须经过IBUF元，否则在布局布线时会报错。IBUFG支持AGP、CTT、GTL、GTLP、HSTL、LVCMOS、LVDCI、LVDS、LVPECL、LVTTL、PCI、PCIX和SSTL等多种格式的IO标准。
2. IBUFGDS是IBUFG的差分形式，当信号从一对差分全局时钟管脚输入时，必须使用IBUFGDS作为全局时钟输入缓冲。IBUFG支持BLVDS、LDT、LVDSEXT、LVDS、LVPECL和ULVDS等多种格式的IO标准。
3. BUFG是全局缓冲，它的输入是IBUFG的输出，BUFG的输出到达FPGA内部的IOB、CLB、选择性块RAM的时钟延迟和抖动最小。
4. BUFGCE是带有时钟使能端的全局缓冲。它有一个输入I、一个使能端CE和一个输出端O。只有当BUFGCE的使能端CE有效(高电平)时，BUFGCE才有输出。
5. BUFGMUX是全局时钟选择缓冲，它有I0和I1两个输入，一个控制端S，一个输出端O。当S为低电平时输出时钟为I0，反之为I1。需要指出的是BUFGMUX的应用十分灵活，I0和I1两个输入时钟甚至可以为异步关系。
6. BUFGP相当于IBUG加上BUFG。
7. BUFGDLL是全局缓冲延迟锁相环，相当于BUFG与DLL的结合。BUFGDLL在早期设计中经常使用，用以完成全局时钟的同步和驱动等功能。随着数字时钟管理单元(DCM)的日益完善，目前BUFGDLL的应用已经逐渐被DCM所取代。 (Q08. DCM即数字时钟管理单元，主要完成时钟的同步、移相、分频、倍频和去抖动等。DCM与全局时钟有着密不可分的联系，为了达到最小的延迟和抖动，几乎所有的DCM应用都要使用全局缓冲资源。DCM可以用Xilinx ISE软件中的Architecture Wizard直接生成。
全局时钟资源的使用方法全局时钟资源的使用方法(五种) 1：IBUFG + BUFG的使用方法： IBUFG后面连接BUFG的方法是最基本的全局时钟资源使用方法，由于IBUFG组合BUFG相当于BUFGP，所以在这种使用方法也称为BUFGP方法。
2. IBUFGDS + BUFG的使用方法： (C8t0a8Uu0当输入时钟信号为差分信号时，需要使用IBUFGDS代替IBUFG。
3. IBUFG + DCM + BUFG的使用方法：这种使用方法最灵活，对全局时钟的控制更加有效。通过DCM模块不仅仅能对时钟进行同步、移相、分频和倍频等变换，而且可以使全局时钟的输出达到无抖动延迟。
4. Logic ＋ BUFG的使用方法： BUFG不但可以驱动IBUFG的输出，还可以驱动其它普通信号的输出。当某个信号(时钟、使能、快速路径)的扇出非常大，并且要求抖动延迟最小时，可以使用BUFG驱动该信号，使该信号利用全局时钟资源。但需要注意的是，普通IO的输入或普通片内信号进入全局时钟布线层需要一个固有的延时，一般在10ns左右，即普通IO和普通片内信号从输入到BUFG输出有一个约10ns左右的固有延时，但是BUFG的输出到片内所有单元(IOB、CLB、选择性块RAM)的延时可以忽略不计为“0”ns。
5． Logic + DCM + BUFG的使用方法：DCM同样也可以控制并变换普通时钟信号，即DCM的输入也可以是普通片内信号。使用全局时钟资源的注意事项全局时钟资源必须满足的重要原则是：使用IBUFG或IBUFGDS的充分必要条件是信号从专用全局时钟管脚输入。换言之，当某个信号从全局时钟管脚输入，不论它是否为时钟信号，都必须使用IBUFG或IBUFGDS；如果对某个信号使用了IBUFG或IBUFGDS硬件原语，则这个信号必定是从全局时钟管脚输入的。如果违反了这条原则，那么在布局布线时会报错。这条规则的使用是由FPGA的内部结构决定的：IBUFG和IBUFGDS的输入端仅仅与芯片的专用全局时钟输入管脚有物理连接，与普通IO和其它内部CLB等没有物理连接。另外，由于BUFGP相当于IBUFG和BUFG的组合，所以BUFGP的使用也必须遵循上述的原则。
全局时钟资源的例化方法全局时钟资源的例化方法大致可分为两种：一是在程序中直接例化全局时钟资源；二是通过综合阶段约束或者实现阶段约束实现对全局时钟资源的使用；第一种方法比较简单，用户只需按照前面讲述的5种全局时钟资源的基本使用方法编写代码或者绘制原理图即可。
第二方法是通过综合阶段约束或实现阶段的约束完成对全局时钟资源的调用，这种方法根据综合工具和布局布线工具的不同而异。

Timing Paths in Design Compiler

2007-11-06T19:07:00.000+08:00

*Start Points:
1.Input ports
2.Clock pins of sequential devices
*End Points:
1.Output ports
2.Data input pins of sequential devices

关于芯片内部SRAM的使用

2007-11-06T19:06:00.000+08:00

1.宽度的影响：SRAM越宽，对面积的影响越大，影响layout。
2.深度的影响：SRAM越深，Timing越差。
建议根据需要合理安排深度和宽度。

ISE批处理方式

2007-11-06T19:03:00.000+08:00

说明：
1.此文件用于将edf网表文件到FPGA的bit文件产生；
2.将注释里面的内容复制到一个bat文件中，保存即可；
3.可用于固化设计环境或者计划任务等。

/**************************/
path ISE_Install_Path/bin/nt
ngdbuild -intstyle xflow -verbose -dd ./_ngo -uc *.ucf -sd /MACRO_PATH -p xc4vlx200-ff1513-10 design_name.edf design_name.ngdmap -intstyle xflow -p xc4vlx200-ff1513-10 -cm balance -pr b -k 4 -c 99 -tx off -o design_name_map.ncd design_name.ngd design_name.pcf par -w -intstyle xflow -ol high -t 1 design_name_map.ncd design_nameip.ncd design_name.pcftrce -intstyle xflow -e 3 -l 3 -xml design_name design_name.ncd -o design_name.twr design_name.pcfbitgen -w design_name.ncd
/**************************/

注释：
line1:path ISE 命令文件的路径，以确保下面的命令能被windows正常调用，会batch的人都知道；
line2:将edf转化成ISE能识别的ndg格式，读取ucf文件；
line3:map过程，将电路网表映射到FPGA内部逻辑单元的网表，产生.ncd和pcf文件；
line4:par，Place and Route，布局布线，使用到map产生的ncd和pcf文件；
line5:trce，产生时序报告
line6:bitgen，产生bit文件

详细命令参数可参阅ISE的UserGuide。

在Linux或者Unix下面运行时候除第一行有差别之外，其他等同。

FPGA入门学习方法

2007-11-06T19:01:00.000+08:00

a)首先学习FPGA的datasheet和userguide，一定要仔细看下来，第一次看也许会有点难度，但坚持下来好处多多。
b)原理图学习，一般学习者手上都有开发板，可以拿现成的板子来学习。一般来说，FPGA板级主要分三部分，配置（JTAG or Parallel，.etc）、时钟、IO。配置部分就是TCLK,TRST,TDI,TDO,TMS和Ground6根线（JTAG方式，Xilinx），时钟对于一般初学者使用的开发板来说才一到两个，一般来说就是接FPGA的GCLK（全局时钟资源）输入。假如时钟输入不是接的全局时钟管脚，在设计时需特别处理。IO部分的话主要就是参考电压，即Ref**的管脚，该部分涉及到各Bank的电平标准设置，对于初学者，且无特殊使用时可以暂先不管。
c)工具的学习。强烈建议看工具的帮助文件，Tutorial，Manual，User Guide等，不要怕太多，英文看不懂，只要坚持过一次，以后就会轻松很多。
d)设计流程。从Coding ->Simulation ->Synthesis ->Implement ->Configuration ->Download。用于初学的设计要简单，且能在开发板上看到效果，如设计一个计数器，让一个LED闪烁。采用HDL的话需要注意可综合的问题。
e)报告分析。这点很关键，而且往往被初学者忽视。一般来说那些报告文件都是文本格式，虽然后缀名不是txt，但用文本编辑器都是可以打开的，如UltraEdit。当然，直接用工具打开是肯定可以的。报告中不懂的东西可以从软件的Manual或者Userguide中间能够找到，找不到的话google也可以。说到google，顺便提两句搜索的技巧，如果想搜索技术方面的东西的话，最好是google，关键字最好是英文的，而且最好不要是很通俗的，如果你要搜索的关键字是很通俗的话，建议再加一个该方面常用的专业词汇。
f)问题解决方法。关于碰到问题该怎么办，很多人第一选择可能就是去论坛发帖或者google。本人是不太喜欢去论坛发帖求教，一是实时性太差，往往等好几天还不一定有人帮你回答，二是论坛中的高手往往是喜欢交流，而不是一味地教导别人。所以，要在论坛发问，最起码你要具备交流的资格，能很清楚地描述你的问题，能说清楚你对于此问题采取过的努力及取得的成效。最忌的是漫无边际地提问，如"我正在学习FPGA，请高手教我该怎么做？"。Google答案我认为是一种比较快捷的手段，也是我平时学习工作采取最多的方法之一。不过正统的办法是自己思考问题，从理论上去找到解决该问题的办法。这点往往也是初学者所缺乏的。

Blog Backup

2007-11-06T11:49:00.000+08:00

This is a backup for http://www.yanzhi.org/blog/

关于

2007-11-02T14:58:00.002+08:00

这是一个 WordPress 页面范例，您可以编辑本页面并增加您或者网站的信息，这样访问者便可知道您来自何方。您可以创建类似本页面的任意多的页面或者子页面，并通过 WordPress 来管理。